公开(公告)号：US20200185501A1

公开(公告)日：2020-06-11

申请号：US16341010

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Gilbert W. Dewey ,  Aaron D. Lilak ,  Justin R. Weber ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/40 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.

公开(公告)号：US20200044059A1

公开(公告)日：2020-02-06

申请号：US16341020

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Aaron D. Lilak ,  Justin R. Weber ,  Harold W. Kennel ,  Willy Rachmady ,  Gilbert W. Dewey ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06

Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.

公开(公告)号：US20200035839A1

公开(公告)日：2020-01-30

申请号：US16043593

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Van H. Le ,  Abhishek A. Sharma ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Miriam R. Reshotko ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.

公开(公告)号：US20200027883A1

公开(公告)日：2020-01-23

申请号：US16495600

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Ravi Pillarisetty ,  Gilbert W. Dewey ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Tahir Ghani

IPC: H01L27/108 ,  H01L29/786 ,  H01L27/12

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

公开(公告)号：US20190097293A1

公开(公告)日：2019-03-28

申请号：US16186103

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Henning Braunisch ,  Gilbert W. Dewey ,  Telesphor Kamgaing ,  Hyung-Jin Lee ,  Johanna M. Swan

IPC: H01P3/127 ,  H01P3/10 ,  H01P5/103

Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.

公开(公告)号：US20220375916A1

公开(公告)日：2022-11-24

申请号：US17323425

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert W. Dewey ,  Jack T. Kavalieros ,  Abhishek A. Sharma ,  Willy Rachmady

IPC: H01L25/18 ,  H01L25/065 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Described herein are IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a compute die, a multilayer memory structure, and an oxide bonding interface coupling the compute die to the multilayer memory structure. The oxide bonding interface includes metal interconnects and an oxide material surrounding the metal interconnects and bonding the compute die to the memory structure.

公开(公告)号：US20220028998A1

公开(公告)日：2022-01-27

申请号：US17498614

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Gilbert W. Dewey ,  Rafael Rios ,  Van H. Le ,  Jack T. Kavalieros

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

公开(公告)号：US11004982B2

公开(公告)日：2021-05-11

申请号：US16495600

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Ravi Pillarisetty ,  Gilbert W. Dewey ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Tahir Ghani

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

公开(公告)号：US10992017B2

公开(公告)日：2021-04-27

申请号：US16192293

申请日：2018-11-15

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01P5/08 ,  H01P3/16 ,  H01P1/208 ,  H01L23/66 ,  H01L25/065 ,  H01P5/107 ,  H01L23/00

Abstract: Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed.

公开(公告)号：US10964820B2

公开(公告)日：2021-03-30

申请号：US16461522

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert W. Dewey ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L27/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24

Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.