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公开(公告)号:US10455063B2
公开(公告)日:2019-10-22
申请号:US15677564
申请日:2017-08-15
Applicant: Intel Corporation
Inventor: Cristian Florin F. Dumitrescu , Namakkal N. Venkatesan , Pierre Laurent , Bruce Richardson
IPC: H04L29/06 , H04L12/743 , H04L12/64
Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.
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公开(公告)号:US10372668B2
公开(公告)日:2019-08-06
申请号:US15870632
申请日:2018-01-12
Applicant: INTEL CORPORATION
Inventor: Chang Yong Kang , Pierre Laurent , Hari K. Tadepalli , Prasad M. Ghatigar , T.J. O'Dwyer , Serge Zhilyaev
Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
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公开(公告)号:US10341264B2
公开(公告)日:2019-07-02
申请号:US15199110
申请日:2016-06-30
Applicant: Intel Corporation
Inventor: John J. Browne , Tomasz Kantecki , Chris MacNamara , Pierre Laurent , Sean Harte
IPC: H04L12/879 , H04L12/43 , H04L12/927 , H04L12/935 , H04L12/861
Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.
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公开(公告)号:US10216483B2
公开(公告)日:2019-02-26
申请号:US15696036
申请日:2017-09-05
Applicant: Intel Corporation
Inventor: T. J. O'Dwyer , Pierre Laurent
IPC: G06F7/523
Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
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公开(公告)号:US10200410B2
公开(公告)日:2019-02-05
申请号:US15282564
申请日:2016-09-30
Applicant: INTEL CORPORATION
Inventor: Michael Hingston McLaughlin Bursell , Stephen T. Palermo , Chris MacNamara , Pierre Laurent , John J. Browne
IPC: H04L29/06
Abstract: A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system permits the rotation of the system security controller among at least a portion of the peer devices. Each of the peer devices uses a defined trust assessment ruleset to determine whether the system security controller is trusted/trustworthy. An untrusted system security controller peer device is replaced by another of the peer devices selected by the peer devices. The current system security controller peer device transfers system threat information and security risk information collected from the peer devices to the new system security controller elected by the peer devices.
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公开(公告)号:US20190007330A1
公开(公告)日:2019-01-03
申请号:US15635581
申请日:2017-06-28
Applicant: Intel Corporation
Inventor: John J. Browne , Tomasz Kantecki , Chris Macnamara , Pierre Laurent , Sean Harte , Peter McCarthy , Jacqueline F. Jardim , Liang Ma
IPC: H04L12/873 , H04L12/883 , H04L12/879 , H04L12/927
Abstract: Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel. Other embodiments are described and claimed.
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公开(公告)号:US09778910B2
公开(公告)日:2017-10-03
申请号:US14664669
申请日:2015-03-20
Applicant: Intel Corporation
Inventor: T. J. O'Dwyer , Pierre Laurent
Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
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公开(公告)号:US09753692B2
公开(公告)日:2017-09-05
申请号:US14668349
申请日:2015-03-25
Applicant: Intel Corporation
Inventor: T. J. O'Dwyer , Pierre Laurent
CPC classification number: G06F7/523
Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
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