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    Defective bit line management in connection with a memory access
    21.
    发明授权
    Defective bit line management in connection with a memory access 有权

    公开(公告)号：US11429469B2

    公开(公告)日：2022-08-30

    申请号：US17195579

    申请日：2021-03-08

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Ravi H. Motwani ,  Chang Wan Ha

    IPC: G06F11/07 ,  G11C16/34 ,  G11C7/12 ,  G11C16/14 ,  G11C29/44

    Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

    Permutation of bit locations to reduce recurrence of bit error patterns in a memory device
    24.
    发明授权
    Permutation of bit locations to reduce recurrence of bit error patterns in a memory device 有权

    公开(公告)号：US11086714B2

    公开(公告)日：2021-08-10

    申请号：US16578039

    申请日：2019-09-20

    Applicant: Intel Corporation

    Inventor： Ravi H. Motwani ,  Zion S. Kwok

    IPC: G06F11/00 ,  G06F11/10 ,  G06F7/58 ,  G06F7/76 ,  H03M13/11

    Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device.

    MITIGATING SILENT DATA CORRUPTION IN ERROR CONTROL CODING
    26.
    发明申请
    MITIGATING SILENT DATA CORRUPTION IN ERROR CONTROL CODING 审中-公开

    公开(公告)号：US20190102248A1

    公开(公告)日：2019-04-04

    申请号：US15721291

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani ,  Zion S. Kwok

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/37

    Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

    ENHANCED ERROR CORRECTING MECHANISM TO PROVIDE RECOVERY FROM MULTIPLE ARBITRARY PARTITION FAILURE
    27.
    发明申请
    ENHANCED ERROR CORRECTING MECHANISM TO PROVIDE RECOVERY FROM MULTIPLE ARBITRARY PARTITION FAILURE 审中-公开

    公开(公告)号：US20180189140A1

    公开(公告)日：2018-07-05

    申请号：US15396525

    申请日：2016-12-31

    Applicant: Intel Corporation

    Inventor： Ravi H. Motwani

    IPC: G06F11/10 ,  H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/116 ,  G06F11/1012 ,  H03M13/373 ,  H03M13/3761

    Abstract: Embodiments are generally directed to an enhanced error correcting mechanism to provide recovery from multiple arbitrary partition failure. An embodiment of a memory device includes a memory controller; multiple memory dies, each memory die including at least two partitions; an error correction code (ECC) circuit block including an ECC encoder and an ECC decoder and corrector, wherein the ECC encoder is to encode data utilizing an LDPC (Low Density Parity Check) code having an H matrix, the LDPC code enabling a single step recovery from a failure of any of the memory dies; and a memory interface. Upon detection of a failure of a first partition of the plurality of memory dies at a first time, the ECC decoder and corrector is to recover data in the memory dies using the data encoded with the LDPC code based on the H matrix. The memory device is to generate a reduced H matrix to remove elements for the first failed partition, and the ECC encoder is to encode data utilizing the LDPC code based on the reduced H matrix.

    Technologies for reducing latency in read operations
    29.
    发明授权
    Technologies for reducing latency in read operations 有权

    公开(公告)号：US09842022B2

    公开(公告)日：2017-12-12

    申请号：US15001358

    申请日：2016-01-20

    Applicant: Intel Corporation

    Inventor： Ravi H. Motwani

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

    CPC classification number: G06F11/1048 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1068 ,  G11C29/021 ,  G11C29/28 ,  G11C29/42 ,  G11C29/52

    Abstract: Technologies for reducing latency in read operations include an apparatus to perform a read attempt of a target data set from a memory, to obtain a candidate data set. A controller performs the read attempt using an initial read parameter, such as an initial read reference voltage. The controller is also to determine a candidate ratio of instances of data values in a portion of the candidate data set, compare the candidate ratio to a predefined reference ratio, determine whether the candidate ratio is within a predefined range of the predefined reference ratio, and, in response to a determination that the candidate ratio is not within the predefined range, adjust the read parameter and perform a subsequent read attempt of the target data set with the adjusted read parameter.

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