公开(公告)号：US20240113009A1

公开(公告)日：2024-04-04

申请号：US17957637

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Whitney Bryks ,  Aaditya Candadai ,  Dilan Seneviratne ,  Junxin Wang ,  Peumie Abeyratne Kuragama

IPC: H01L23/498 ,  B05D3/02 ,  B05D3/04 ,  B05D5/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/538

CPC classification number: H01L23/49894 ,  B05D3/0272 ,  B05D3/0426 ,  B05D5/00 ,  H01L21/481 ,  H01L23/147 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/5384

Abstract: An electronic device can include an interposer, a first porous polymer layer, and one or more die. The interposer can include a metallic through via extending from a first surface of the interposer to a second surface of the interposer. The first polymer layer can be adjacent to the first surface of the interposer. The one or more dies can be coupled to the first porous polymer layer and connected to the metallic through via.

公开(公告)号：US20240112999A1

公开(公告)日：2024-04-04

申请号：US17955689

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Houssam Jomaa ,  Dilan Seneviratne ,  Whitney Bryks ,  Srinivas Venkata Ramanuja Pietambaram ,  Kristof Darmawikarta

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49894

Abstract: An electronic system comprising can have a substrate with a core layer formed from at least one layer of glass. The glass layers can each be stacked with a dielectric material disposed between each layer of glass. The glass layers can be prepatterned before assembly of the layered glass core system.

公开(公告)号：US20230034737A1

公开(公告)日：2023-02-02

申请号：US17389649

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Junxin Wang ,  Whitney Bryks

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC die package including IC die on both a first and second side of an interposer. The backside of first IC die are attached, for example through a direct bond, to a first side of the interposer. Redistribution layer (RDL) metal features are then fabricated, for example with semi-additive processes (SAP), to form interconnects to the frontside of the first die that terminate at first-level interconnect (FLI) interfaces. The frontside of second IC are attached, for example through a direct bond, to a second side of the interposer. Through vias in the interposer couple the second IC die to the first IC die and/or the FLI interfaces. Through vias of the interposer may be coupled to pillars on the first side of the interposer with the first IC die positioned between the pillars, facilitating power delivery to the second IC die.