公开(公告)号：US20230395445A1

公开(公告)日：2023-12-07

申请号：US17833650

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K3/40

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L21/486 ,  H05K1/0306 ,  H05K3/4061

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US20230395467A1

公开(公告)日：2023-12-07

申请号：US17833648

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/03

CPC classification number: H01L23/481 ,  H01L23/49822 ,  H01L23/49816 ,  H01L21/486 ,  H01L21/76898 ,  H05K1/112 ,  H01L24/16 ,  H05K3/429 ,  H05K3/4644 ,  H05K1/0306 ,  H01L2224/16225

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US20220139792A1

公开(公告)日：2022-05-05

申请号：US17085177

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Whitney Bryks ,  Sarah Blythe ,  Peumie Abeyratne Kuragama ,  Junxin Wang

IPC: H01L23/29 ,  H01L23/18 ,  H01L23/31 ,  H01L23/522

Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.

公开(公告)号：US20240113009A1

公开(公告)日：2024-04-04

申请号：US17957637

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Whitney Bryks ,  Aaditya Candadai ,  Dilan Seneviratne ,  Junxin Wang ,  Peumie Abeyratne Kuragama

IPC: H01L23/498 ,  B05D3/02 ,  B05D3/04 ,  B05D5/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/538

CPC classification number: H01L23/49894 ,  B05D3/0272 ,  B05D3/0426 ,  B05D5/00 ,  H01L21/481 ,  H01L23/147 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/5384

Abstract: An electronic device can include an interposer, a first porous polymer layer, and one or more die. The interposer can include a metallic through via extending from a first surface of the interposer to a second surface of the interposer. The first polymer layer can be adjacent to the first surface of the interposer. The one or more dies can be coupled to the first porous polymer layer and connected to the metallic through via.

公开(公告)号：US20230034737A1

公开(公告)日：2023-02-02

申请号：US17389649

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Junxin Wang ,  Whitney Bryks

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC die package including IC die on both a first and second side of an interposer. The backside of first IC die are attached, for example through a direct bond, to a first side of the interposer. Redistribution layer (RDL) metal features are then fabricated, for example with semi-additive processes (SAP), to form interconnects to the frontside of the first die that terminate at first-level interconnect (FLI) interfaces. The frontside of second IC are attached, for example through a direct bond, to a second side of the interposer. Through vias in the interposer couple the second IC die to the first IC die and/or the FLI interfaces. Through vias of the interposer may be coupled to pillars on the first side of the interposer with the first IC die positioned between the pillars, facilitating power delivery to the second IC die.