公开(公告)号：US12087700B2

公开(公告)日：2024-09-10

申请号：US17391905

申请日：2021-08-02

申请人： Intel Corporation

发明人： Srinivas Venkata Ramanuja Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0652 ,  H01L23/5221 ,  H01L23/5381 ,  H01L24/16 ,  H01L2224/023 ,  H01L2224/0233 ,  H01L2224/16235

摘要： Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US11637171B2

公开(公告)日：2023-04-25

申请号：US16934873

申请日：2020-07-21

申请人： Intel Corporation

发明人： Shivasubramanian Balasubramanian ,  Dilan Seneviratne

IPC分类号： H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  H01L27/08

摘要： A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.

公开(公告)号：US20210260718A1

公开(公告)日：2021-08-26

申请号：US16797925

申请日：2020-02-21

申请人： INTEL CORPORATION

发明人： Srini Raghavan ,  Sashi Shekhar Kandanur ,  Rahul N. Manepalli ,  Ravindranadh T. Eluri ,  Dilan Seneviratne ,  Clark Linde ,  ABDIAS J. ACOSTA ,  Francoise Bainye Angoua

IPC分类号： B24B37/04 ,  B24B37/20

摘要： A polishing tool and methodology are disclosed, particularly useful for chemical mechanical polish (CMP) applications (e.g., polishing and planarizing). In an embodiment, the tool includes a carrier structure configured to support a workpiece, a polishing pad configured to rotate and polish at least a portion of the workpiece, a source configured to generate excitation radiation directed towards the workpiece, and a detector configured to receive fluorescence radiation from the workpiece. The fluorescence radiation is generated by absorption of the excitation radiation by a polymer material on the workpiece. The polishing tool also includes a controller configured to, based on a magnitude of the received fluorescence radiation, change at least one operating condition of the polishing tool. For instance, the controller can speed or slow the polishing process, and stop the polishing process when a target thickness is achieved.

公开(公告)号：US10985080B2

公开(公告)日：2021-04-20

申请号：US15778042

申请日：2015-11-24

申请人： Intel Corporation

发明人： Pramod Malatkar ,  Kyle Yazzie ,  Naga Sivakumar Yagnamurthy ,  Richard J. Harries ,  Dilan Seneviratne ,  Praneeth Akkinepally ,  Xuefei Wan ,  Yonggang Li ,  Robert L. Sankman

IPC分类号： H01L23/31 ,  H01L23/34 ,  H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

摘要： An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.

公开(公告)号：US10546916B2

公开(公告)日：2020-01-28

申请号：US16024223

申请日：2018-06-29

申请人： Intel Corporation

发明人： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC分类号： H01L29/00 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

摘要： Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20200006468A1

公开(公告)日：2020-01-02

申请号：US16024223

申请日：2018-06-29

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC分类号： H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

摘要： Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20200006463A1

公开(公告)日：2020-01-02

申请号：US16020271

申请日：2018-06-27

申请人： Intel Corporation

发明人： Shivasubramanian Balasubramanian ,  Dilan Seneviratne

IPC分类号： H01L49/02 ,  H01L27/08 ,  H01L23/522 ,  H01L23/498

摘要： A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.

公开(公告)号：US20190333861A1

公开(公告)日：2019-10-31

申请号：US16474019

申请日：2017-03-29

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manapalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

摘要： Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US20160329274A1

公开(公告)日：2016-11-10

申请号：US14778987

申请日：2014-12-22

申请人： INTEL CORPORATION

发明人： Wei-Lun Kane Jen ,  Padam Jain ,  Dilan Seneviratne ,  Chi-Mon Chen

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00

CPC分类号： H05K1/0271 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/0044 ,  H05K2201/0191 ,  H05K2201/05 ,  H05K2203/0278 ,  H05K2203/085 ,  H01L2924/00

摘要： Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

摘要翻译： 所公开的实施例包括用于半导体封装的多层衬底。 衬底可以包括第一层，第一层具有xy平面，第一侧上的各个位置具有低于第一侧面xy平面的第一侧面距离，第二侧面具有第二面xy平面和各个位置 在第二侧上可以具有在第二侧面xy平面下方的第二侧面距离; 以及第二层，其具有耦合到第一层的第二侧的第一侧和与第二层的第一侧相对的第二侧，其中第二层上的各个位置处的第二层的厚度可以由 第一侧距离加上第二边距离。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160284630A1

公开(公告)日：2016-09-29

申请号：US14653033

申请日：2014-07-11

申请人： INTEL CORPORATION

发明人： Alejandro Levander ,  Tatyana Andryushchenko ,  David Staines ,  Mauro Kobrinsky ,  Aleksandar Aleksov ,  Dilan Seneviratne ,  Javier Soto Gonzalez ,  Srinivas Pietambaram ,  Rafiqul Islam

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/4985 ,  B23B5/16 ,  B32B27/08 ,  B32B27/283 ,  B32B2307/54 ,  B32B2307/7265 ,  B32B2439/00 ,  B32B2457/00 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/48227 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0715 ,  H01L2924/15747 ,  H01L2924/15791 ,  H05K1/0283 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

摘要翻译： 这里通常讨论的是可以包括可拉伸和可弯曲装置的系统和方法。 根据一个实例，一种方法可以包括（1）在面板上沉积第一弹性体材料，（2）在弹性体材料上层叠微量材料，（3）处理微量材料以将痕量材料图案化成一个或多个迹线 或更多的接合垫，（4）将管芯附接到所述一个或多个接合焊盘，或（5）在所述一个或多个迹线上和周围沉积第二弹性体材料，所述接合焊盘和所述管芯以将所述一个或多个 迹线和第一和第二弹性体材料中的一个或多个接合焊盘。