公开(公告)号：US20190042422A1

公开(公告)日：2019-02-07

申请号：US15927715

申请日：2018-03-21

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen

IPC: G06F12/0811 ,  G06F12/0804

Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

公开(公告)号：US20190004952A1

公开(公告)日：2019-01-03

申请号：US15636072

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Nagi Aboulenein

IPC: G06F12/0846 ,  G06F12/128

Abstract: An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

公开(公告)号：US09583182B1

公开(公告)日：2017-02-28

申请号：US15077424

申请日：2016-03-22

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zhe Wang ,  Zeshan A. Chishti

IPC: G11C16/04 ,  G11C11/56

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

Abstract translation: 多级存储器管理电路可重新映射近端和远端存储器之间的数据。 在一个实施例中，寄存器阵列存储映射到近存储器地址的近地址和远的存储器地址。 寄存器数组中的条目数量小于近内存中的页数。 重映射逻辑确定所请求数据的远存储器地址不存在于寄存器阵列中，并从寄存器阵列中选择可用的近地址。 重映射逻辑还启动在远存储器地址处将所请求的数据写入所选择的近地址。 重映射逻辑进一步将远存储器地址写入对应于所选择的近似存储器地址的寄存器阵列的条目。