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    Vector processor supporting linear interpolation on multiple dimensions
    21.
    发明授权
    Vector processor supporting linear interpolation on multiple dimensions 有权

    公开(公告)号：US12106101B2

    公开(公告)日：2024-10-01

    申请号：US17131939

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Joseph Williams ,  Zoran Zivkovic

    IPC: G06F9/30 ,  G06F9/38 ,  G06F16/901

    CPC classification number: G06F9/30036 ,  G06F9/3812 ,  G06F9/3873 ,  G06F16/9017

    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

    Multicore synchronization mechanism for time critical radio systems
    22.
    发明授权
    Multicore synchronization mechanism for time critical radio systems 有权

    公开(公告)号：US12072835B2

    公开(公告)日：2024-08-27

    申请号：US17851739

    申请日：2022-06-28

    Applicant: Intel Corporation

    Inventor： Kevin Kinney ,  Zoran Zivkovic

    IPC: G06F15/80 ,  G06F1/12

    CPC classification number: G06F15/80 ,  G06F1/12

    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.

    HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
    24.
    发明公开
    HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE 审中-公开

    公开(公告)号：US20230205730A1

    公开(公告)日：2023-06-29

    申请号：US17560637

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Zoran Zivkovic ,  Kameran Azadet ,  Kannan Rajamani ,  Thomas Smith

    IPC: G06F15/80 ,  G06F17/11

    CPC classification number: G06F15/8092 ,  G06F17/11

    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

    DIGITAL PRE-DISTORTION (DPD) ADAPTATION USING A HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
    25.
    发明公开
    DIGITAL PRE-DISTORTION (DPD) ADAPTATION USING A HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE 审中-公开

    公开(公告)号：US20230205727A1

    公开(公告)日：2023-06-29

    申请号：US17560685

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Zoran Zivkovic ,  Kameran Azadet ,  Kannan Rajamani ,  Thomas Smith

    IPC: G06F15/80 ,  G06F1/26

    CPC classification number: G06F15/80 ,  G06F1/26

    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

    Apparatus and method for controlling complex multiply-accumulate circuitry
    26.
    发明授权
    Apparatus and method for controlling complex multiply-accumulate circuitry 有权

    公开(公告)号：US11474825B2

    公开(公告)日：2022-10-18

    申请号：US16367193

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： Zoran Zivkovic

    IPC: G06F7/544 ,  G06F9/38 ,  G06F9/30

    Abstract: An apparatus and method for performing multiply-accumulate (MAC) operations on complex numbers to generate real results. For example, one embodiment of a processor comprises: a decoder to decode instructions including multiply-accumulate instructions; first and second source registers to store a first plurality of complex values and a second plurality of complex values, respectively, each complex value comprising a real value and an imaginary value; multiply-accumulate (MAC) execution circuitry coupled to the first and second source registers comprising multiplier circuitry, adder circuitry, and accumulator circuitry; mode selection circuitry to select between at least two execution modes for the MAC execution circuitry including a first mode in which the MAC execution circuitry is to perform complex multiply-accumulate operations using real and imaginary values from the first plurality of complex values and the second plurality of complex values and a second mode in which the MAC execution circuitry is to replace one or more of the real or imaginary values from the first and second plurality of complex values with one or more real or imaginary values specified in a set of scalar complex numbers or with zeroes.

    Enhanced frequency offset tracking in optical signals
    28.
    发明授权
    Enhanced frequency offset tracking in optical signals 有权

    公开(公告)号：US10790900B2

    公开(公告)日：2020-09-29

    申请号：US16233940

    申请日：2018-12-27

    Applicant: Intel Corporation

    Inventor： Javier Perez-Ramirez ,  Spencer Markowitz ,  Zoran Zivkovic ,  Nagarajan Muralidharan ,  Ankitkumar Navik ,  Rufeng Meng ,  Richard Roberts

    IPC: H04B10/079 ,  H04B10/516 ,  H04N5/455

    Abstract: This disclosure describes systems, methods, and devices related to frequency offset tracking in optical signals. A device may identify modulated light received from a light source, wherein the modulated light is received at a frame rate, and wherein the modulated light is associated with pixel clusters. The device may determine light samples based on the pixel clusters, the light samples including a first light sample and a second light sample. The device may determine a vector norm between the first light sample and the second light sample using an oversampling factor. The device may determine that the vector norm is below a threshold. The device may determine a start frame delimiter (SFD) based on the vector norm. The device may demodulate the symbol based on the oversampling factor.

    Augmented reality depth sensing using dual camera receiver
    29.
    发明授权
    Augmented reality depth sensing using dual camera receiver 有权

    公开(公告)号：US10586394B2

    公开(公告)日：2020-03-10

    申请号：US15909759

    申请日：2018-03-01

    Applicant: INTEL CORPORATION

    Inventor： Javier Perez-Ramirez ,  Spencer Markowitz ,  Zoran Zivkovic

    IPC: G06T19/00 ,  G01S17/10 ,  G06T15/20 ,  G06F3/01 ,  G06K9/62 ,  G02B27/01 ,  G06T7/593 ,  G01S11/12 ,  G01S5/16 ,  G06K9/00 ,  G06F3/147 ,  G06F3/14

    Abstract: An example apparatus for depth sensing includes an image data receiver to receive image data from a communication camera and an augmented reality (AR) camera. The apparatus also includes a modulated light detector to detect one or more modulated lights in the image data from the communication camera. The apparatus further includes a representation generator to generate a visual representation of a local image region for each of the detected modulated lights. The apparatus includes a region matcher to match the visual representation for each of the detected modulated lights with a region in the image data received from the AR camera. The apparatus also further includes a distance estimator to estimate a distance between a dual camera receiver and the one or more modulated lights based on a disparity between a position of the visual representation and a position of the matched region in the image data.

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