公开(公告)号：US20240220445A1

公开(公告)日：2024-07-04

申请号：US18147829

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Kameran Azadet ,  Kevin Kinney ,  Thomas Smith ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F15/80 ,  G06F9/5027 ,  G06F9/54

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of DPD terms. The architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.

公开(公告)号：US10911680B2

公开(公告)日：2021-02-02

申请号：US16235715

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Gregoire Kerr ,  Zoran Zivkovic

IPC: H04N5/232 ,  H04N5/353 ,  G06T3/00 ,  G06T7/80 ,  G06T5/00 ,  G06T7/13 ,  G06T7/00 ,  G06T7/70

Abstract: A method, system, and article is directed to geolocation and attitude correction for mobile rolling shutter cameras.

公开(公告)号：US10749502B2

公开(公告)日：2020-08-18

申请号：US15721555

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Zoran Zivkovic ,  Edwin Van Dalen

IPC: H03H17/06 ,  G06F17/15 ,  G06F9/30 ,  G06F9/38 ,  H03H17/00 ,  H03H17/02

Abstract: An apparatus and method for performing FIR filtering and blending operations. A processor comprising: a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; and an execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N−1 multiplications to generate at least N−1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed data elements, the execution unit to combine the at least N−1 products in accordance with a specified type of FIR filter being implemented to generate a result packed data element to be stored in the destination storage location.

公开(公告)号：US10594952B2

公开(公告)日：2020-03-17

申请号：US15927503

申请日：2018-03-21

Applicant: Intel Corporation

Inventor： Zoran Zivkovic

IPC: H04N5/262 ,  H04N5/232 ,  H04N5/235

Abstract: Systems, devices, and techniques related to selecting a key frame for burst image processing are discussed. Such techniques may include generating key frame scores for at least some frames of a multi-frame burst image capture such that the key frame scores include a combination of an image quality component, a shutter lag component, and a burst image processing latency component and selecting a frame having a maximum key frame score as the key frame.

公开(公告)号：US12282774B2

公开(公告)日：2025-04-22

申请号：US17358231

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joseph Williams ,  Zoran Zivkovic ,  Jian-Guo Chen ,  Hong Wan ,  David Dougherty ,  Jay O'neill

IPC: G06F9/30

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

公开(公告)号：US20240220249A1

公开(公告)日：2024-07-04

申请号：US18147099

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David Dougherty ,  Madihally Narasimha ,  Joseph Othmer ,  Hong Wan ,  Joseph Williams ,  Zoran Zivkovic

IPC: G06F9/30 ,  G06F30/343

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F30/343

Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.

公开(公告)号：US20240104049A1

公开(公告)日：2024-03-28

申请号：US18529363

申请日：2023-12-05

Applicant: Intel Corporation

Inventor： Erik Rijshouwer ,  Jeroen Leijten ,  Bert Schellekens ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/80 ,  G06F9/30098

Abstract: Techniques are disclosed for a programmable processor array architecture that enables synchronized broadcasting of operation results to register files with the operation results. The architecture advantageously enables writing of operation results of a given operation to multiple destination registers in a single clock cycle for processors with partitioned register files by using common data stationary instruction encoding. This combination brings improved performance by reducing the need for costly copy operations that would otherwise occupy issue slots and thus schedule space while at the same time minimizing code size overhead. The performance gains of broadcasting are especially emphasized in highly parallel and heavily partitioned register file architectures.

公开(公告)号：US20220197640A1

公开(公告)日：2022-06-23

申请号：US17131939

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Joseph Williams ,  Zoran Zivkovic

IPC: G06F9/30 ,  G06F9/38 ,  G06F16/901

Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

公开(公告)号：US20210019565A1

公开(公告)日：2021-01-21

申请号：US17063414

申请日：2020-10-05

Applicant: Intel Corporation

Inventor： Aleksandar Sutic ,  Zoran Zivkovic ,  Gilad Michael

IPC: G06K9/62 ,  G06N5/04 ,  G06T1/00 ,  G06K9/66 ,  G06T5/00 ,  G06N3/04

Abstract: In an example method for training image signal processors, a reconstructed image is generated via an image signal processor based on a sensor image. An intermediate loss function is generated based on a comparison of an output of one or more corresponding layers of a computer vision network and a copy of the computer vision network. The output of the computer vision network is based on the reconstructed image. An image signal processor is trained based on the intermediate loss function.

公开(公告)号：US09916531B1

公开(公告)日：2018-03-13

申请号：US15629981

申请日：2017-06-22

Applicant: INTEL CORPORATION

Inventor： Zoran Zivkovic ,  Barry de Bruin

IPC: G06N3/08 ,  G06N3/04 ,  H04N19/126

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  H04N19/126

Abstract: An apparatus is described herein. The apparatus comprises an accumulator, a controller, and a convolutional neural network. The accumulator is to accumulate a plurality of values within a predetermined bit width. The controller is to determine a parameter quantization and a data quantization. The convolutional neural network is adapted to the data quantization, wherein a quantization point is selected based on the parameter quantization, data quantization, and accumulator bit width.