公开(公告)号：US20140129773A1

公开(公告)日：2014-05-08

申请号：US14070639

申请日：2013-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christian Habermann ,  Christian Jacobi ,  Martin Recktenwald ,  Hans-Werner Tast

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0824 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/622

Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.

Abstract translation: 分级缓存结构包括至少一个高级缓存，其包括用于数据和指令的统一高速缓存阵列和至少两个较低级别的高速缓存，每个高级缓存分别在指令高速缓存和数据高速缓存中。 分裂的第二级高速缓存的指令高速缓存和数据高速缓存连接到第三级高速缓存; 并且分离的第一级高速缓存的指令高速缓存连接到分离的第二级高速缓存的指令高速缓存，并且分离的第一级高速缓存的数据高速缓存连接到指令高速缓存和分离的第二级高速缓存的数据高速缓存。

公开(公告)号：US20140082293A1

公开(公告)日：2014-03-20

申请号：US13621256

申请日：2012-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Khary J. ALexander ,  Christian Jacobi ,  Gerrit Koch ,  Martin Recktenwald ,  Timothy J. Slegel ,  Hans-Werner Tast

IPC: G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/467

Abstract: Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation.

Abstract translation: 提供了与处理器一起处理存储缓冲器的技术，该存储缓冲器包括一个空闲列表; 合并窗口 和驱逐名单; 和逻辑，因为在接收到T_STORE操作时，将与T_STORE操作相关联的第一地址与与先前T_STORE操作相关联的多个地址进行比较，其中先前的T_STORE操作是与T_STORE操作相同的事务的一部分，并且条目 对应于先前的T_STORE操作存储在合并窗口中; 响应于所述多个地址中的与第二T_STORE操作相关联的第一地址和第二地址之间的匹配，将与第一T_STORE操作相对应的第一条目与对应于第二T_STORE操作的第二条目合并; 并且与第一个T_STORE操作相关联的结果合并与第二个T_STORE操作相关联的结果。

公开(公告)号：US20130339616A1

公开(公告)日：2013-12-19

申请号：US13788200

申请日：2013-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Khary J. Alexander ,  Christian Jacobi ,  Hans-Werner Tast ,  Patrick M. West

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F9/467 ,  G06F11/1474 ,  G06F12/0828

Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.