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公开(公告)号:US20230269253A1
公开(公告)日:2023-08-24
申请号:US17652302
申请日:2022-02-24
Applicant: International Business Machines Corporation
Inventor: Daniel Pittner , Martin Smolny , Christian Habermann , Silke Wastl , Michael Haide
IPC: H04L9/40 , H04L41/0654
CPC classification number: H04L63/102 , H04L63/1458 , H04L63/126 , H04L41/0654
Abstract: Embodiments of the present invention provide computer-implemented methods, computer program products and computer systems for enabling modifying a behavior of a consuming component. The method comprises requesting a smart client by a consuming component. The smart client is adapted to modify a control logic of the consuming component and to establish a network connection. Next, the consuming component executes the smart client and receives a modification for the smart client of the consuming component. Further, a computer-implemented method for enabling modifying a behavior of a consuming component by a serving component is disclosed. This method comprises, upon receiving a request for a smart client by the serving component, providing a smart client, transmitting the smart client, receiving service requests comprising procedure calls to be executed by the serving component, and, upon detecting a performance change by the serving component, sending a modification for the smart client.
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公开(公告)号:US20210306438A1
公开(公告)日:2021-09-30
申请号:US16834754
申请日:2020-03-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Sven Sterbling , Christian Habermann , Sachin Lingadahalli Vittal
Abstract: A method, computer system, and a computer program product for execution of a stateless service on a node in a workload execution environment is provided. The present invention may include defining for each node a workload container including a cache component of a cache-mesh. The present invention may include, upon receiving a state request from a stateless requesting service from one of the cache components of the cache-mesh in an execution container, determining whether a requested state is present in the cache component of a related execution container. The present invention may include, upon a cache miss, broadcasting the state request to other cache components of the cache-mesh, determining, by the other cache components, whether the requested state is present in respective caches, and upon any cache component identifying the requested state, sending the requested state to the requesting service using a protocol for communication.
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公开(公告)号:US20170220439A1
公开(公告)日:2017-08-03
申请号:US15197534
申请日:2016-06-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Christian Habermann , Gerrit Koch , Martin Recktenwald , Ralf Winkelmann
IPC: G06F11/263 , G06F11/22 , G06F12/08
CPC classification number: G06F11/0724 , G06F11/141 , G06F11/1474 , G06F11/2242 , G06F11/261 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F2212/1032 , G06F2212/452 , G06F2212/6042 , G06F2212/621
Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.
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公开(公告)号:US20140129774A1
公开(公告)日:2014-05-08
申请号:US14070692
申请日:2013-11-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Christian Habermann , Christian Jacobi , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/08
CPC classification number: G06F12/0897 , G06F12/0811 , G06F2212/1024 , G06F2212/604
Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.
Abstract translation: 分级缓存结构包括至少一个具有目录的真实索引高级缓存和用于数据和指令的统一高速缓存阵列,以及至少两个低级高速缓存,每个低级缓存分别在指令高速缓存和数据高速缓存中。 分割的实际索引的二级高速缓存的指令高速缓存包括连接到实际索引的第三级高速缓存的目录和对应的高速缓存阵列。 分离的第二级高速缓存的数据高速缓存包括连接到第三级高速缓存的目录。 分割的虚拟索引的第一级高速缓存的指令高速缓存连接到第二级指令高速缓存。 第一级高速缓存的数据高速缓存的高速缓存阵列连接到第二级指令高速缓存的高速缓存阵列和第三级高速缓存的高速缓存阵列。 第一级数据高速缓存的目录连接到第二级指令高速缓存目录和第三级缓存目录。
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公开(公告)号:US20170220437A1
公开(公告)日:2017-08-03
申请号:US15010088
申请日:2016-01-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Christian Habermann , Gerrit Koch , Martin Recktenwald , Ralf Winkelmann
IPC: G06F11/263 , G06F11/22 , G06F12/08
CPC classification number: G06F11/0724 , G06F11/141 , G06F11/1474 , G06F11/2242 , G06F11/261 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F2212/1032 , G06F2212/452 , G06F2212/6042 , G06F2212/621
Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.
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公开(公告)号:US09384131B2
公开(公告)日:2016-07-05
申请号:US13843278
申请日:2013-03-15
Applicant: International Business Machines Corporation
Inventor: Christian Habermann , Christian Jacobi , Sascha Junghans , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0862 , G06F12/0897 , G06F2212/1024
Abstract: Systems and methods for providing data from a cache memory to requestors includes a number of cache memory levels arranged in a hierarchy. The method includes receiving a request for fetching data from the cache memory and determining one or more addresses in a cache memory level which is one level higher than a current cache memory level using one or more prediction algorithms. Further, the method includes pre-fetching the one or more addresses from the high cache memory level and determining if the data is available in the addresses. If data is available in the one or more addresses then data is fetched from the high cache level, else addresses of a next level which is higher than the high cache memory level are determined and pre-fetched. Furthermore, the method includes providing the fetched data to the requestor.
Abstract translation: 用于从缓存存储器向请求者提供数据的系统和方法包括以层级布置的多个高速缓存存储器级。 该方法包括从高速缓冲存储器接收数据取出请求,并使用一个或多个预测算法确定高于当前高速缓存存储器级别的一级的高速缓冲存储器级别中的一个或多个地址。 此外,该方法包括从高速缓冲存储器级别预取一个或多个地址,并确定该地址中的数据是否可用。 如果数据在一个或多个地址中可用,则从高高速缓存级别获取数据,否则确定并预取高于高缓存存储器级别的下一级的地址。 此外,该方法包括将提取的数据提供给请求者。
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公开(公告)号:US09323673B2
公开(公告)日:2016-04-26
申请号:US14070639
申请日:2013-11-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Christian Habermann , Christian Jacobi , Martin Recktenwald , Hans-Werner Tast
CPC classification number: G06F12/0811 , G06F12/0824 , G06F12/0846 , G06F12/0848 , G06F12/0875 , G06F12/0897 , G06F2212/283 , G06F2212/452 , G06F2212/622
Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.
Abstract translation: 分级缓存结构包括至少一个高级缓存,其包括用于数据和指令的统一高速缓存阵列和至少两个较低级别的高速缓存,每个高级缓存分别在指令高速缓存和数据高速缓存中。 分裂的第二级高速缓存的指令高速缓存和数据高速缓存连接到第三级高速缓存; 并且分离的第一级高速缓存的指令高速缓存连接到分离的第二级高速缓存的指令高速缓存,并且分离的第一级高速缓存的数据高速缓存连接到指令高速缓存和分离的第二级高速缓存的数据高速缓存。
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公开(公告)号:US20250156227A1
公开(公告)日:2025-05-15
申请号:US18408696
申请日:2024-01-10
Applicant: International Business Machines Corporation
Inventor: Daniel Pittner , Benjamin Isinger , Christian Habermann , Sugandha Agrawal , Jeremias Werner
IPC: G06F9/50
Abstract: A method for reduced latency between software services operating in a service mesh, where the software services are instantiated when fulfilling requests is disclosed. The method comprises providing a plurality of services which fulfill a request, where communication between the services is based on support components, The method also comprises creating a directed dependency graph of the plurality of services by tracing request flows between the plurality of services, thereby nodes of the directed dependency graph represent services and edges of the directed dependency graph represent used communication paths between selected ones of the services, determining a dependent service for an incoming request to a selected one of the plurality of services based on the directed dependency graph, and starting an instance of the dependent service together with the selected one of the plurality of services.
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公开(公告)号:US09928127B2
公开(公告)日:2018-03-27
申请号:US15010088
申请日:2016-01-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Christian Habermann , Gerrit Koch , Martin Recktenwald , Ralf Winkelmann
IPC: G06F11/00 , G06F11/07 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F11/22 , G06F11/14 , G06F11/26
CPC classification number: G06F11/0724 , G06F11/141 , G06F11/1474 , G06F11/2242 , G06F11/261 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F12/0875 , G06F12/0891 , G06F12/0897 , G06F2212/1032 , G06F2212/452 , G06F2212/6042 , G06F2212/621
Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.
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公开(公告)号:US09665486B2
公开(公告)日:2017-05-30
申请号:US15093088
申请日:2016-04-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Christian Habermann , Christian Jacobi , Martin Recktenwald , Hans-Werner Tast
IPC: G06F3/00 , G06F9/46 , G06F12/0811 , G06F12/0846 , G06F12/0897 , G06F12/0817 , G06F12/0875
CPC classification number: G06F12/0811 , G06F12/0824 , G06F12/0846 , G06F12/0848 , G06F12/0875 , G06F12/0897 , G06F2212/283 , G06F2212/452 , G06F2212/622
Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.
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