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21.发明申请Sense amplifier with reduced current consumption for semiconductors memories 有权具有减少电流消耗的半导体存储器的感应放大器公开(公告)号：US20070242541A1
公开(公告)日：2007-10-18
申请号：US11726993
申请日：2007-03-23
申请人： Michele La Placa , Ignazio Martines
发明人： Michele La Placa , Ignazio Martines
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C11/5642 , G11C16/28 , G11C2207/063
摘要： A sensing circuit for a semiconductor memory, comprising at least one detecting amplifier, said detecting amplifier comprising: a first circuital branch adapted to be electrically run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current, said cell current being a function of a state of a memory cell to be read in a predetermined biasing condition; a second circuital branch coupled as a current mirror configuration with the first circuital branch, said second circuital branch being adapted in the operation to be run through by a third current proportional to the first current; a third circuital branch coupled to said second branch, said third circuital branch being adapted in the operation to sink a fourth current as a function of said comparison current; a fourth circuital branch coupled to said second and third circuital branches, said fourth circuital branch being adapted in the operation to be run through by a residual current equal to the difference between the third and the fourth current, said residual current assuming different values depending on the fact that the cell current is lower, equal or higher than the comparison current; residual current sensitive means adapted to generate an indication of the state of the memory cell as a function of a value of the residual current.
摘要翻译： 一种用于半导体存储器的感测电路，包括至少一个检测放大器，所述检测放大器包括：第一电路分支，其适于电流通过对应于作为比较电流的函数的第二电流的和的第一电流;以及 电池电流，所述电池电流是在预定偏置条件下要读取的存储器单元的状态的函数; 第二电路分支作为具有第一电路分支的电流反射镜配置耦合，所述第二电路分支适于在与第一电流成比例的第三电流的运行中运行; 耦合到所述第二分支的第三电路分支，所述第三电路分支适于作为所述比较电流的函数来吸收第四电流的操作; 耦合到所述第二和第三电路分支的第四电路分支，所述第四电路分支适于在所述操作中运行等于所述第三和第四电流之间的差的剩余电流，所述剩余电流取决于 电池电流低于等于或高于比较电流的事实; 剩余电流敏感装置适于根据剩余电流的值产生存储器单元的状态的指示。
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22.发明申请公开(公告)号：US20070210839A1
公开(公告)日：2007-09-13
申请号：US11717853
申请日：2007-03-13
申请人： Ignazio Martines , Michele La Placa
发明人： Ignazio Martines , Michele La Placa
IPC分类号： H03B1/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2207/2254
摘要： An output buffer for providing a buffered current to a circuit load includes a plurality of operative stages, each one for generating a component of the buffered current and an enabling circuit for selectively enabling each operative stage. The output buffer further comprises at least one auxiliary stage and control means for measuring a control current that can be delivered by the at least one auxiliary stage and for activating the enabling means according to the measured control current.
摘要翻译： 用于向电路负载提供缓冲电流的输出缓冲器包括多个操作级，每个操作级用于产生缓冲电流的分量，以及使能电路，用于选择性地使能每个操作级。 输出缓冲器还包括至少一个辅助级和控制装置，用于测量可由至少一个辅助级传递的控制电流，并根据测量的控制电流激活使能装置。
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23.发明授权Method and device for fast addressing redundant columns in a nonvolatile memory 失效在非易失性存储器中快速寻址冗余列的方法和设备公开(公告)号：US06310801B1
公开(公告)日：2001-10-30
申请号：US09548783
申请日：2000-04-13
IPC分类号： G11C1624
摘要： A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.
摘要翻译： 一种用于寻址非易失性存储器中的冗余列的方法，其在输入处接收选择地址并且包括多个冗余列，每个冗余列包括连接到位线的相应位线和多个存储器单元。 寻址方法包括以下步骤：检测选择地址中的转换; 在检测到地址中的转换时，开始对所有位线进行充电; 然后检测冗余列之一是否被寻址; 如果发现冗余列中的一个被寻址，继续对寻址的冗余列的位线进行充电，并且中断对未被寻址的冗余列的位线的充电; 并且不应发现冗余列被寻址，中断所有位线的充电。
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公开(公告)号：US20070024123A1
公开(公告)日：2007-02-01
申请号：US11444287
申请日：2006-05-31
IPC分类号： H02M3/06
摘要： An architecture for implementing an integrated capacity advantageously includes a capacitive block inserted between a first and a second voltage reference. The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.
摘要翻译： 用于实现集成容量的架构有利地包括插入在第一和第二电压参考之间的电容性块。 该块由基本电容模块形成。 在第一电压基准和电容性块之间插入使能块，并且包括连接到基本电容模块并通过控制信号在其控制端子上驱动的开关。 使能块的每个开关插入在第一参考电压和对应的基本电容模块的第一端之间。 验证和使能电路连接到第一参考电压以及基本电容模块的第一端的输入端以及使能块的开关的控制端子的输出。 验证和使能电路检测每个基本电容模块中是否存在电流值，并且如果检测到所述电流，则使用使能块的相应开关禁用电容块的基本电容模块。
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公开(公告)号：US6097633A
公开(公告)日：2000-08-01
申请号：US182843
申请日：1998-10-29
申请人： Michele La Placa
发明人： Michele La Placa
摘要： A read circuit for non-volatile memories having an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline. A differential amplifier for comparing voltage signals obtained by current/voltage conversion of a current signal of an array cell and of a reference current signal is connected to the respective bit lines. A cascode transistor for each one of the array and reference sections, each driven by a NOR logic gate; a charge transistor for the bitline and a charge transistor for the reference bitline; column decoding transistors for the array section and for the reference section; the circuit further comprising an additional transistor which is connected between the NOR gate of the array side and a node for acquiring the array voltage sent to the differential amplifier, the additional transistor increasing the speed of the process for reading the bitline when the bitline is not charged.
摘要翻译： 具有具有相应位线的阵列部分和具有相应参考位线的参考部分的非易失性存储器的读取电路。 用于比较通过阵列单元的电流信号的电流/电压转换获得的电压信号和参考电流信号的差分放大器连接到各个位线。 用于阵列和参考部分中的每一个的共源共栅晶体管，每个由NOR逻辑门驱动; 用于位线的充电晶体管和用于参考位线的充电晶体管; 用于阵列部分和参考部分的列解码晶体管; 该电路还包括连接在阵列侧的或非门之间的附加晶体管和用于获取发送到差分放大器的阵列电压的节点，附加晶体管增加了当位线不是时读取位线的处理速度 带电。
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公开(公告)号：US07414459B2
公开(公告)日：2008-08-19
申请号：US11444287
申请日：2006-05-31
IPC分类号： H02M3/06
摘要： An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage reference. The block is formed The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.
摘要翻译： 用于实现集成容量的架构包括插入在第一和第二电压基准之间的电容性块。 该块由基本电容模块形成。 在第一电压基准和电容性块之间插入使能块，并且包括连接到基本电容模块并通过控制信号在其控制端子上驱动的开关。 使能块的每个开关插入在第一参考电压和对应的基本电容模块的第一端之间。 验证和使能电路连接到第一参考电压以及基本电容模块的第一端的输入端以及使能块的开关的控制端子的输出。 验证和使能电路检测每个基本电容模块中是否存在电流值，并且如果检测到所述电流，则使用使能块的相应开关禁用电容块的基本电容模块。
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公开(公告)号：US20060164888A1
公开(公告)日：2006-07-27
申请号：US11262294
申请日：2005-10-28
IPC分类号： G11C16/04
摘要： A voltage-down converter for providing an output voltage lower than a power supply voltage of the converter is proposed. The converter includes voltage regulation means for obtaining an intermediate voltage corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element with a control signal resulting from a comparison between the intermediate voltage and a reference voltage, and an output stage for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set of multiple basic modules, the converter further including means for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.
摘要翻译： 提出了一种用于提供低于转换器的电源电压的输出电压的降压转换器。 转换器包括电压调节装置，用于通过由中间电压和参考电压之间的比较产生的控制信号控制可变电导率元件，从而获得与电源电压相对应的输出电压的中间电压，以及用于 通过利用所述控制信号控制另外的可变导电性元件从所述电源电压获得所述输出电压，其中所述另外的可变导电元件具有至少一组多个基本模块的模块化结构，所述转换器还包括用于使能 和/或根据输出电压和中间电压之间的比较来连续地禁用每组的模块。
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公开(公告)号：US20060103453A1
公开(公告)日：2006-05-18
申请号：US11258825
申请日：2005-10-26
IPC分类号： G05F1/10
摘要： A voltage down converter is provided that includes a voltage regulator and voltage driver circuit branches. The voltage regulator receives a first voltage, has a regulation node providing a regulated second voltage that is lower than the first voltage, and has a control node providing a control voltage corresponding to the second voltage. One voltage driver circuit branch receives the first voltage and includes a variable-conductivity element having a control terminal coupled to the control node for controlling a current sunk by the variable-conductivity element. This one voltage driver circuit branch has a voltage supply node supplying a down-converted voltage corresponding to the second voltage. At least one additional voltage driver circuit branch receives the first voltage and is coupled to the voltage supply node. The additional voltage driver circuit branch includes a further variable-conductivity element having a control terminal coupled to the control node for controlling a current sunk by the further variable-conductivity element, and a switching circuit for selectively enabling the further variable-conductivity element so as to keep the down-converted voltage at a prescribed value depending on the regulated second voltage.
摘要翻译： 提供了一个降压转换器，它包括一个稳压器和电压驱动电路分支。 电压调节器接收第一电压，具有提供低于第一电压的调节的第二电压的调节节点，并且具有提供对应于第二电压的控制电压的控制节点。 一个电压驱动器电路分支接收第一电压并且包括具有耦合到控制节点的控制端子的可变导电性元件，用于控制由可变导电性元件引起的电流下降。 该一个电压驱动器电路分支具有提供对应于第二电压的下变频电压的电压供应节点。 至少一个附加的电压驱动器电路分支接收第一电压并耦合到电压供应节点。 附加电压驱动器电路分支包括另外的可变导电元件，其具有耦合到控制节点的控制端子，用于控制由另外的可变导电性元件引起的电流下降;以及开关电路，用于选择性地使能另外的可变导电性元件，使得 以根据调节的第二电压将下变频电压保持在规定值。
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公开(公告)号：US07385377B2
公开(公告)日：2008-06-10
申请号：US11262294
申请日：2005-10-28
摘要： A voltage-down converter for providing an output voltage lower than a power supply voltage of the converter is proposed. The converter includes voltage regulation means for obtaining an intermediate voltage corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element with a control signal resulting from a comparison between the intermediate voltage and a reference voltage, and an output stage for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set of multiple basic modules, the converter further including means for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.
摘要翻译： 提出了一种用于提供低于转换器的电源电压的输出电压的降压转换器。 转换器包括电压调节装置，用于通过由中间电压和参考电压之间的比较产生的控制信号控制可变电导率元件，从而获得与电源电压相对应的输出电压的中间电压，以及用于 通过利用所述控制信号控制另外的可变导电性元件从所述电源电压获得所述输出电压，其中所述另外的可变导电元件具有至少一组多个基本模块的模块化结构，所述转换器还包括用于使能 和/或根据输出电压和中间电压之间的比较来连续地禁用每组的模块。
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公开(公告)号：US07167394B2
公开(公告)日：2007-01-23
申请号：US11121616
申请日：2005-05-04
IPC分类号： G11C11/34
CPC分类号： G11C16/28
摘要： A sense amplifier for reading a non-volatile memory cell includes a bitline current path connected to a non-volatile memory cell to be read, and a reference current path connected to a reference memory cell. A current mirror includes an input transistor and a corresponding input node, and an output transistor and a corresponding output node. The current mirror converts currents in the reference current path and the bitline current path to respective voltages on the input and output nodes. An equalization circuit equalizes the voltages on the input and output nodes of the current mirror and is activated by a command signal. The equalization circuit includes a switch controlled by the command signal, and a diode-connected load transistor connected in parallel to the output transistor of the current mirror and connected to the output node thereof through the switch. A current steering path draws from the bitline current path a current when enabled by the command signal so that the load transistor establishes a desired voltage on the output node.
摘要翻译： 用于读取非易失性存储单元的读出放大器包括连接到要读取的非易失性存储器单元的位线电流路径和连接到参考存储器单元的参考电流路径。 电流镜包括输入晶体管和相应的输入节点，以及输出晶体管和相应的输出节点。 电流镜将参考电流路径中的电流和位线电流路径转换为输入和输出节点上的相应电压。 均衡电路均衡电流镜的输入和输出节点上的电压，并由命令信号激活。 均衡电路包括由指令信号控制的开关和与电流镜的输出晶体管并联连接的二极管连接的负载晶体管，并通过开关连接到其输出节点。 当命令信号使能时，当前的转向路径从位线电流通路中抽出电流，使得负载晶体管在输出节点上建立所需的电压。
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