-
公开(公告)号：US07218135B2
公开(公告)日：2007-05-15
申请号：US11163015
申请日：2005-09-30
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00346
摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。
-
公开(公告)号：US08077534B2
公开(公告)日：2011-12-13
申请号：US12183099
申请日：2008-07-31
IPC分类号： G11C7/02
摘要： A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.
摘要翻译： 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。
-
公开(公告)号：US20100031067A1
公开(公告)日：2010-02-04
申请号：US12183099
申请日：2008-07-31
IPC分类号： G06F1/03
摘要： A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.
摘要翻译： 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。
-
24.发明申请ENVIRONMENTAL AND COMPUTING COST REDUCTION WITH IMPROVED RELIABILITY IN WORKLOAD ASSIGNMENT TO DISTRIBUTED COMPUTING NODES 有权环境和计算成本降低，在分配计算节点的工作量分配中具有改进的可靠性公开(公告)号：US20100228861A1
公开(公告)日：2010-09-09
申请号：US12397897
申请日：2009-03-04
申请人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, JR. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
发明人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, JR. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
IPC分类号： G06F9/50 , G06F9/46 , G06F15/16 , G06F15/173
CPC分类号： G06F9/5027 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.
摘要翻译： 一种将计算任务的作业提交分配给每个具有至少一个处理实体的分布式服务器场集合的系统和方法; 从至少一个处理实体接收工作负载请求以提交给所述一组分布式服务器场中的至少一个; 使用与计算任务相关联的至少一个或多个条件来接受或拒绝要分配作业提交的至少一个服务器场; 确定可优化一个或多个条件的服务器场; 以及将所述作业提交分发到所述服务器场，所述服务器场优化与所述计算任务相关联并用于选择所述至少一个所述服务器场的所述一个或多个条件中的至少一个。
-
25.发明授权Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes 有权降低环境和计算成本，提高分布式计算节点工作负载分配的可靠性公开(公告)号：US08793365B2
公开(公告)日：2014-07-29
申请号：US12397897
申请日：2009-03-04
申请人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, Jr. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
发明人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, Jr. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
IPC分类号： G06F15/173
CPC分类号： G06F9/5027 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.
摘要翻译： 一种将计算任务的作业提交分配给每个具有至少一个处理实体的分布式服务器场集合的系统和方法; 从至少一个处理实体接收工作负载请求以提交给所述一组分布式服务器场中的至少一个; 使用与计算任务相关联的至少一个或多个条件来接受或拒绝要分配作业提交的至少一个服务器场; 确定可优化一个或多个条件的服务器场; 以及将所述作业提交分发到所述服务器场，所述服务器场优化与所述计算任务相关联并用于选择所述至少一个所述服务器场的所述一个或多个条件中的至少一个。
-
公开(公告)号：US20080046772A1
公开(公告)日：2008-02-21
申请号：US11457916
申请日：2006-07-17
IPC分类号： G06F1/00
CPC分类号： G06F1/10
摘要： A method and system for reducing clock noises are disclosed. A clock signal includes active edges and inactive edges. Inactive edges produce clock noise but are not critical to the functionality of the clock signal. That is, only active edges are critical to proper timing of an integrated circuit (IC). As such, inactive edges of clock signals to clocked elements of an IC may be shifted to be misaligned to one another. As a consequence, peak noise produced by the inactive edges will be spread over a large area and therefore will be reduced in amplitude.
摘要翻译： 公开了一种减少时钟噪声的方法和系统。 时钟信号包括有效边沿和非活动边沿。 无效边沿产生时钟噪声，但并不对时钟信号的功能至关重要。 也就是说，只有有效边沿对于集成电路（IC）的正确定时至关重要。 因此，到IC的时钟元件的时钟信号的无效边沿可能被移位以彼此不对准。 结果，由无源边缘产生的峰值噪声将在大面积上扩展，因此幅度将被减小。
-
公开(公告)号：US07743270B2
公开(公告)日：2010-06-22
申请号：US11530544
申请日：2006-09-11
CPC分类号： G06F1/04 , G06F1/10 , G06F17/5031 , G06F17/505 , G06F2217/62
摘要： A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
摘要翻译： 公开了减少由集成电路（IC）中的时钟信号产生的时钟噪声的方法，系统和计算机程序产品。 传统IC设计尝试确保所有时钟元件的重合时钟主动边沿到达时间。 重合的有效时钟边沿产生一致的噪声电流，这提高了总的噪声电流。 本发明基于期望的时钟到达时间分布来为IC的时钟元件分配时钟到达时间，使得活动时钟边缘不一致。 因此，总噪声将在时钟周期的大部分时间内扩展，从而大大降低噪声幅度。
-
公开(公告)号：US20090102529A1
公开(公告)日：2009-04-23
申请号：US11876871
申请日：2007-10-23
IPC分类号： H03K3/017
摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: multiple clocked elements; a clock signal source providing clock signals to the multiple clocked elements; and a clock shifting means coupled between the clock signal source and each of the multiple clocked elements; wherein the clock shifting means shifts clock signals of the multiple clocked elements such that the clock signals of the multiple clocked elements have aligned active edges and misaligned inactive edges to reduce the clock noise generated by the inactive edges of the clock signals.
摘要翻译： 公开了集成电路和设计结构。 集成电路可以包括：多个时钟元件; 时钟信号源，向多个时钟元件提供时钟信号; 以及时钟移位装置，其耦合在所述时钟信号源与所述多个时钟元件中的每一个之间; 其中所述时钟移位装置移动所述多个时钟元件的时钟信号，使得所述多个时钟元件的时钟信号具有对准的有源边沿和未对准的非有效边沿，以减少由所述时钟信号的不活动边缘产生的时钟噪声。
-
公开(公告)号：US20080065923A1
公开(公告)日：2008-03-13
申请号：US11530544
申请日：2006-09-11
IPC分类号： G06F1/12
CPC分类号： G06F1/04 , G06F1/10 , G06F17/5031 , G06F17/505 , G06F2217/62
摘要： A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
摘要翻译： 公开了减少由集成电路（IC）中的时钟信号产生的时钟噪声的方法，系统和计算机程序产品。 传统IC设计尝试确保所有时钟元件的重合时钟主动边沿到达时间。 重合的有效时钟边沿产生一致的噪声电流，这提高了总噪声电流。 本发明基于期望的时钟到达时间分布来为IC的时钟元件分配时钟到达时间，使得活动时钟边缘不一致。 因此，总噪声将在时钟周期的大部分时间内扩展，从而大大降低噪声幅度。
-
公开(公告)号：US07705626B2
公开(公告)日：2010-04-27
申请号：US11847362
申请日：2007-08-30
申请人： Igor Arsovski , Joseph A. Iadanza
发明人： Igor Arsovski , Joseph A. Iadanza
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00346 , H03K17/162
摘要： A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译： 公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的设计结构。 IC芯片与主电源通信并且包括至少一个电压岛。 芯片的电压岛上的主要头部通过主头电源路径与主电源通信。 芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。 与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。
-
-
-
-
-
-
-
-
-
搜索结果
99 条记录 (耗时 0.101 秒)
