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93 条记录 (耗时 0.036 秒)

    Method and apparatus for reducing noise in a dynamic manner
    24.
    发明授权
    Method and apparatus for reducing noise in a dynamic manner 有权
    以动态方式降低噪音的方法和装置

    公开(公告)号：US07218135B2

    公开(公告)日：2007-05-15

    申请号：US11163015

    申请日：2005-09-30

    申请人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    IPC分类号： H03K19/003 ,  H03K17/16

    CPC分类号： H03K19/00346

    摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

    摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

    Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees
    27.
    发明申请
    Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
    用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法

    公开(公告)号：US20080143416A1

    公开(公告)日：2008-06-19

    申请号：US11610848

    申请日：2006-12-14

    申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F1/04 ,  G06F1/10

    CPC分类号： G06F1/10

    摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

    摘要翻译： 公开了一种用于提供平衡负载的时钟分配网络，结构和方法。 特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
    28.
    发明申请
    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
    用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构

    公开(公告)号：US20080229265A1

    公开(公告)日：2008-09-18

    申请号：US12129748

    申请日：2008-05-30

    申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G06F17/5045

    摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

    摘要翻译： 公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。 特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

    System and method for balancing delay of signal communication paths through well voltage adjustment
    29.
    发明授权
    System and method for balancing delay of signal communication paths through well voltage adjustment 有权
    通过井电压调整来平衡信号通信路径的延迟的系统和方法

    公开(公告)号：US07404114B2

    公开(公告)日：2008-07-22

    申请号：US10906343

    申请日：2005-02-15

    申请人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    发明人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    IPC分类号： G01R31/28

    CPC分类号： H03K5/133 ,  H03K2005/00032

    摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

    摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

    Structure and method for providing gate leakage isolation locally within analog circuits
    30.
    发明授权
    Structure and method for providing gate leakage isolation locally within analog circuits 失效
    在模拟电路中局部提供栅极泄漏隔离的结构和方法

    公开(公告)号：US07268632B2

    公开(公告)日：2007-09-11

    申请号：US11163013

    申请日：2005-09-30

    申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    IPC分类号： H03L7/00 ,  H03L7/099 ,  H03B5/18

    CPC分类号： H03L7/093 ,  H03L7/0891

    摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

    摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。