公开(公告)号：US11095556B2

公开(公告)日：2021-08-17

申请号：US15639393

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US11005692B2

公开(公告)日：2021-05-11

申请号：US16902151

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L27/01 ,  H04L25/03

Abstract: A port of a computing device is to connect to another device over a link and use equalization logic to perform equalization of the link at a plurality of different data rates. The equalization logic may identify that the other device supports bypassing a sequential equalization mode, determine a maximum data rate supported by the devices on the link, and participate in equalization of the link at the maximum supported data rate before equalizing the link at one or more other data rates lower than the maximum supported data rate in the plurality of data rates.

公开(公告)号：US10997111B2

公开(公告)日：2021-05-04

申请号：US16439582

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/42

Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme. The assembled flits can be transmitted across one or more serial point-to-point interconnects in a link connecting the transmitting device to a receiving device. The protocol stack can protect flit information sent across each point-to-point interconnect with a lane-level interleaved forward error correction (FEC) scheme.

公开(公告)号：US20210109879A1

公开(公告)日：2021-04-15

申请号：US17132132

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/40 ,  G06F12/1072 ,  G06F13/16 ,  G06F13/42 ,  G06F15/167

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

公开(公告)号：US20210081288A1

公开(公告)日：2021-03-18

申请号：US17106946

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Daniel S. Froelich

IPC: G06F11/22 ,  G06F13/42

Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

公开(公告)号：US20210042248A1

公开(公告)日：2021-02-11

申请号：US17076739

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0811 ,  G06F13/40

Abstract: Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.

公开(公告)号：US20200374037A1

公开(公告)日：2020-11-26

申请号：US16991681

申请日：2020-08-12

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L1/00

Abstract: Systems and devices can include a first port of a first device coupled to a second port of a second device across a multi-lane link. The first port can augment a data block with error correcting code by distributing error correcting code evenly across each lane of the data block, wherein each lane of the data block includes a same number of error correcting code. The first port can transmit the data block with the per-lane error correcting code to the second port across the multi-lane link. The second port can determine error correcting code based on the error correcting code bits received in the data block, and perform error correction on the symbols of the data block based on the error correcting code received.

公开(公告)号：US10784986B2

公开(公告)日：2020-09-22

申请号：US15640449

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L1/00

Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.

公开(公告)号：US10606785B2

公开(公告)日：2020-03-31

申请号：US16171342

申请日：2018-10-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20190303342A1

公开(公告)日：2019-10-03

申请号：US16446470

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.