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    Remote atomic operations in multi-socket systems
    1.
    发明授权
    Remote atomic operations in multi-socket systems 有权

    公开(公告)号：US11537520B2

    公开(公告)日：2022-12-27

    申请号：US17494651

    申请日：2021-10-05

    Applicant: Intel Corporation

    Inventor： Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jonas Svennebring ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  David A. Koufaty

    IPC: G06F12/0815 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0817 ,  G06F12/0831

    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

    REMOTE ATOMIC OPERATIONS IN MULTI-SOCKET SYSTEMS
    3.
    发明申请
    REMOTE ATOMIC OPERATIONS IN MULTI-SOCKET SYSTEMS 有权

    公开(公告)号：US20220091983A1

    公开(公告)日：2022-03-24

    申请号：US17494651

    申请日：2021-10-05

    Applicant: Intel Corporation

    Inventor： Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jonas Svennebring ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  David A. Koufaty

    IPC: G06F12/0815 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0817

    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

    TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS
    4.
    发明申请
    TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS 有权

    公开(公告)号：US20210399982A1

    公开(公告)日：2021-12-23

    申请号：US17391557

    申请日：2021-08-02

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

    IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

    SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS
    5.
    发明申请
    SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS 审中-公开

    公开(公告)号：US20200319886A1

    公开(公告)日：2020-10-08

    申请号：US16799619

    申请日：2020-02-24

    Applicant: Intel Corporation

    Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

    IPC: G06F9/30 ,  G06F12/0875

    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

    SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS
    8.
    发明申请
    SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS 审中-公开
    规范机制，以实施向地址写入的监视器的指令

    公开(公告)号：US20150095580A1

    公开(公告)日：2015-04-02

    申请号：US14040375

    申请日：2013-09-27

    Applicant: Intel Corporation

    Inventor： Yen-Cheng Liu ,  Bahaa Fahim ,  Erik G. Hallnor ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren ,  Antonio Juan

    IPC: G06F12/08

    Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

    Abstract translation: 处理器包括对应于分布式高速缓存的第一高速缓存部分的高速缓存器侧地址监视器单元，其具有小于处理器的逻辑处理器总数的高速缓存器侧地址监视器存储位置的总数。 每个缓存侧地址监视器存储位置是存储要监视的地址。 核心侧地址监视器单元对应于第一核心，并且具有与第一核心的多个逻辑处理器相同数量的核心侧地址监视器存储位置。 每个核心侧地址监视器存储位置用于存储第一核心的不同对应逻辑处理器的地址和监视状态。 高速缓存侧地址监视器存储溢出单元对应于第一高速缓存部分，并且当没有未使用的高速缓存侧地址监视器存储位置可用于存储要监视的地址时，强制执行地址监视器存储溢出策略。

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