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    Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm
    28.
    发明授权
    Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm 有权
    用于计算多轮skein散列算法的执行单元的装置和方法

    公开(公告)号：US09569210B2

    公开(公告)日：2017-02-14

    申请号：US15203610

    申请日：2016-07-06

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

    IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

    CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

    Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

    Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到所述第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）置换逻辑电路，其具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入。

    Methods, systems and apparatus to reduce processor demands during encryption
    29.
    发明授权
    Methods, systems and apparatus to reduce processor demands during encryption 有权
    加密过程中减少处理器需求的方法，系统和设备

    公开(公告)号：US09461816B2

    公开(公告)日：2016-10-04

    申请号：US13727141

    申请日：2012-12-26

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

    IPC: H04L29/00 ,  H04L9/06 ,  G06F9/00 ,  G06F21/00

    CPC classification number: H04L9/0637 ,  G06F9/00 ,  G06F9/30032 ,  G06F21/00 ,  H04L2209/12

    Abstract: Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher.

    Abstract translation: 公开了减少加密期间处理器需求的方法和装置。 所公开的示例方法包括：检测处理器执行确定加密密码是否与字节反射操作相关联的加密密码的请求，当与加密密码相关联的缓冲器不会导致携带条件时，防止字节反射操作;以及 在执行加密密码之前通过移位操作递增缓冲区。

    Method and Apparatus to Process 4-Operand SIMD Integer Multiply-Accumulate Instruction
    30.
    发明申请
    Method and Apparatus to Process 4-Operand SIMD Integer Multiply-Accumulate Instruction 审中-公开
    处理4-操作数SIMD整数乘法累加指令的方法和装置

    公开(公告)号：US20160202975A1

    公开(公告)日：2016-07-14

    申请号：US15077093

    申请日：2016-03-22

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: G06F9/30

    CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/3887

    Abstract: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.

    Abstract translation: 根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。 第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。 所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到 基于第四操作数的累计值。

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