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21.发明授权公开(公告)号：US09588771B2
公开(公告)日：2017-03-07
申请号：US13791298
申请日：2013-03-08
Applicant: Intel Corporation
Inventor： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
CPC classification number: G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器相对于指令定序器是异质资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。
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公开(公告)号：US12141683B2
公开(公告)日：2024-11-12
申请号：US17246341
申请日：2021-04-30
Applicant: Intel Corporation
Inventor： Arnab Raha , Debabrata Mohapatra , Gautham Chinya , Guruguhanathan Venkataramanan , Sang Kyun Kim , Deepak Mathaikutty , Raymond Sung , Cormac Brick
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.
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公开(公告)号：US20220108093A1
公开(公告)日：2022-04-07
申请号：US17554255
申请日：2021-12-17
Applicant: Intel Corporation
Inventor： Gautham Chinya , Shihao Ji , Arnab Paul
Abstract: Systems, apparatuses and methods may provide for replacing floating point matrix multiplication operations with an approximation algorithm or computation in applications that involve sparse codes and neural networks. The system may replace floating point matrix multiplication operations in sparse code applications and neural network applications with an approximation computation that applies an equivalent number of addition and/or subtraction operations.
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公开(公告)号：US20210027029A1
公开(公告)日：2021-01-28
申请号：US17067979
申请日：2020-10-12
Applicant: Intel Corporation
Inventor： Gautham Chinya , Shihao Ji , Arnab Paul
Abstract: Systems, apparatuses and methods may provide for replacing floating point matrix multiplication operations with an approximation algorithm or computation in applications that involve sparse codes and neural networks. The system may replace floating point matrix multiplication operations in sparse code applications and neural network applications with an approximation computation that applies an equivalent number of addition and/or subtraction operations.
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Patent Agency Ranking
25.发明授权公开(公告)号：US09990206B2
公开(公告)日：2018-06-05
申请号：US13843164
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Hong Wang , John Shen , Edward Grochowski , Richard Hankins , Gautham Chinya , Bryant Bigbee , Shivnandan Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggawal , Prashant Sethi , Baiju Patel , James Held
CPC classification number: G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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公开(公告)号：US09875102B2
公开(公告)日：2018-01-23
申请号：US15386615
申请日：2016-12-21
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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公开(公告)号：US09766891B2
公开(公告)日：2017-09-19
申请号：US15166469
申请日：2016-05-27
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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公开(公告)号：US09383997B2
公开(公告)日：2016-07-05
申请号：US13914830
申请日：2013-06-11
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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29.发明申请Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource 审中-公开指令集基于异构资源的基于架构的间隔符间通信公开(公告)号：US20150070368A1
公开(公告)日：2015-03-12
申请号：US14541933
申请日：2014-11-14
Applicant: Intel Corporation
Inventor： Hong Wang , John Shen , Hong Jiang , Richard Hankins , Per Hammarlund , Dion Rodgers , Gautham Chinya , Baiju Patel , Shiv Kaushik , Bryant Bigbee , Gad Sheaffer , Yoav Talgam , Yuval Yosef , James P. Held
CPC classification number: G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于在加速器和与其耦合的指令定序器之间直接通信的方法，其中加速器是相对于指令定序器的异构资源。 可以使用接口来提供这些资源之间的通信。 通过这种通信机制，用户级应用可以直接与加速器进行通信，而无需操作系统支持。 此外，指令定序器和加速器可以并行地执行操作。 描述和要求保护其他实施例。
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