公开(公告)号：US20220197719A1

公开(公告)日：2022-06-23

申请号：US17128525

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： STAV GURTOVOY ,  MATEUSZ MARIA PRZYBYLSKI ,  MICHAEL APODACA ,  MANJUNATH DS

IPC: G06F9/52 ,  G06F9/48

Abstract: An apparatus to facilitate thread synchronization is disclosed. The apparatus comprises one or more processors to execute a producer thread to generate a plurality of commands, execute a consumer thread to process the plurality of commands and synchronize the producer thread with the consumer thread, including updating a producer fence value upon generation of in-order commands, updating a consumer fence value upon processing of the in-order commands and performing a synchronization operation based on the consumer fence value, wherein the producer fence value and the consumer fence value each correspond to an order position of an in-order command.

公开(公告)号：US20220182592A1

公开(公告)日：2022-06-09

申请号：US17526633

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20220108518A1

公开(公告)日：2022-04-07

申请号：US17505387

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： KAI XIAO ,  MICHAEL APODACA ,  CARSON BROWNLEE ,  THOMAS RAOUX ,  JOSHUA BARCZAK ,  GABOR LIKTOR

IPC: G06T15/06 ,  G06T1/20

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

公开(公告)号：US20200211262A1

公开(公告)日：2020-07-02

申请号：US16235838

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： KARTHIK VAIDYANATHAN ,  MICHAEL APODACA ,  THOMAS RAOUX ,  CARSTEN BENTHIN ,  KAI XIAO ,  CARSON BROWNLEE ,  JOSHUA BARCZAK

IPC: G06T15/06 ,  G06T1/60

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20200211259A1

公开(公告)日：2020-07-02

申请号：US16235391

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MICHAEL APODACA ,  CARSTEN BENTHIN ,  KAI XIAO ,  CARSON BROWNLEE ,  TIMOTHY ROWLEY ,  JOSHUA BARCZAK ,  TRAVIS SCHLUESSLER

IPC: G06T15/06 ,  G06F7/14 ,  G06F16/901 ,  G06F9/38

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20180012328A1

公开(公告)日：2018-01-11

申请号：US15204402

申请日：2016-07-07

Applicant: Intel Corporation

Inventor： Jeffery S. Boles ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  PRITAV H. SHAH ,  MICHAEL APODACA ,  MURALI RAMADOSS ,  LALIT K. SAPTARSHI

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.