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公开(公告)号：US20200211272A1
公开(公告)日：2020-07-02
申请号：US16235517
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX , CARSON BROWNLEE , GABOR LIKTOR
Abstract: Multi-pass apparatus and method for ray tracing shading. For example, one embodiment of an apparatus comprises: graphics processing circuitry to execute a sequence of visibility testing operations related to texels within a texture domain to generate visibility results; a register or memory to store a texel mask; texel mask update circuitry/logic to update the texel mask based on the visibility results, the texel mask comprising a plurality of bits to indicate visibility of the texels within the texture domain, the texel mask update circuitry/logic to set a first bit to indicate whether any bits in the texel mask indicate a visible texel; a shader dispatcher to initiate conditional dispatch operations only if the first bit is set to indicate that at least one bit in the texel mask indicates a visible texel, wherein to perform the conditional dispatch operations, the shader dispatcher is to dispatch texel shaders for only those texels that the texel mask indicates may be visible; and a plurality of execution units (EUs) to execute the shaders dispatched by the shader dispatcher.
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公开(公告)号：US20210327120A1
公开(公告)日：2021-10-21
申请号：US17308828
申请日：2021-05-05
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , GABOR LIKTOR , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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公开(公告)号：US20200211260A1
公开(公告)日：2020-07-02
申请号：US16235583
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： KAI XIAO , MICHAEL APODACA , CARSON BROWNLEE , THOMAS RAOUX , JOSHUA BARCZAK , GABOR LIKTOR
Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
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Patent Agency Ranking
公开(公告)号：US20200211266A1
公开(公告)日：2020-07-02
申请号：US16236245
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , GABOR LIKTOR , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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公开(公告)号：US20200211231A1
公开(公告)日：2020-07-02
申请号：US16235672
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , CARSTEN BENTHIN , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , PRASOONKUMAR SURTI , THOMAS RAOUX
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US20220108518A1
公开(公告)日：2022-04-07
申请号：US17505387
申请日：2021-10-19
Applicant: Intel Corporation
Inventor： KAI XIAO , MICHAEL APODACA , CARSON BROWNLEE , THOMAS RAOUX , JOSHUA BARCZAK , GABOR LIKTOR
Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
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公开(公告)号：US20200211262A1
公开(公告)日：2020-07-02
申请号：US16235838
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , MICHAEL APODACA , THOMAS RAOUX , CARSTEN BENTHIN , KAI XIAO , CARSON BROWNLEE , JOSHUA BARCZAK
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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公开(公告)号：US20200211259A1
公开(公告)日：2020-07-02
申请号：US16235391
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： MICHAEL APODACA , CARSTEN BENTHIN , KAI XIAO , CARSON BROWNLEE , TIMOTHY ROWLEY , JOSHUA BARCZAK , TRAVIS SCHLUESSLER
IPC: G06T15/06 , G06F7/14 , G06F16/901 , G06F9/38
Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
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