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    TECHNOLOGIES FOR OFFLOAD DEVICE FETCHING OF ADDRESS TRANSLATIONS
    26.
    发明申请
    TECHNOLOGIES FOR OFFLOAD DEVICE FETCHING OF ADDRESS TRANSLATIONS 有权

    公开(公告)号：US20210149815A1

    公开(公告)日：2021-05-20

    申请号：US17129496

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Saurabh Gayen ,  Philip R. Lantz ,  Dhananjay A. Joshi ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Narayan Ranganathan ,  Sanjay Kumar

    IPC: G06F12/10 ,  G06F12/0875 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

    Abstract: Techniques for offload device address translation fetching are disclosed. In the illustrative embodiment, a processor of a compute device sends a translation fetch descriptor to an offload device before sending a corresponding work descriptor to the offload device. The offload device can request translations for virtual memory address and cache the corresponding physical addresses for later use. While the offload device is fetching virtual address translations, the compute device can perform other tasks before sending the corresponding work descriptor, including operations that modify the contents of the memory addresses whose translation are being cached. Even if the offload device does not cache the translations, the fetching can warm up the cache in a translation lookaside buffer. Such an approach can reduce the latency overhead that the offload device may otherwise incur in sending memory address translation requests that would be required to execute the work descriptor.

    Instruction and logic to expose error domain topology to facilitate failure isolation in a processor
    28.
    发明授权
    Instruction and logic to expose error domain topology to facilitate failure isolation in a processor 有权

    公开(公告)号：US10223187B2

    公开(公告)日：2019-03-05

    申请号：US15372734

    申请日：2016-12-08

    Applicant: INTEL CORPORATION

    Inventor： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Vincent J. Zimmer

    IPC: G06F9/30 ,  G06F11/07

    Abstract: A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.

    Mechanism for management controllers to learn the control plane hierarchy in a data center environment
    29.
    发明授权
    Mechanism for management controllers to learn the control plane hierarchy in a data center environment 有权

    公开(公告)号：US09686143B2

    公开(公告)日：2017-06-20

    申请号：US14494892

    申请日：2014-09-24

    Applicant: INTEL CORPORATION

    Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

    IPC: H04L12/24 ,  H04L29/12 ,  H04L12/855

    CPC classification number: H04L41/12 ,  H04L41/044 ,  H04L47/2466 ,  H04L61/2015 ,  H04L61/2507

    Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

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