公开(公告)号：US20200233923A1

公开(公告)日：2020-07-23

申请号：US16839013

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F17/16 ,  G06N3/063 ,  G11C8/08 ,  G11C7/12 ,  G11C7/10 ,  G06F9/30 ,  G11C11/56 ,  G11C11/418 ,  G11C11/419

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

公开(公告)号：US20200098826A1

公开(公告)日：2020-03-26

申请号：US16141025

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Gregory CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Raghavan KUMAR ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Huseyin SUMBUL ,  Ian A. YOUNG

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

公开(公告)号：US20200026498A1

公开(公告)日：2020-01-23

申请号：US16586648

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Raghavan KUMAR ,  Ram KRISHNAMURTHY

IPC: G06F7/544 ,  G06F7/498 ,  G06F17/16 ,  G06F9/30 ,  G06F12/02

Abstract: A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.

公开(公告)号：US20200019847A1

公开(公告)日：2020-01-16

申请号：US16583217

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram KRISHNAMURTHY ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Deepak Vinayak KADETOTAD

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

公开(公告)号：US20200019846A1

公开(公告)日：2020-01-16

申请号：US16583201

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram KRISHNAMURTHY ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/063 ,  G06F7/523 ,  G06F7/509 ,  G06F9/30 ,  G06F9/38

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

公开(公告)号：US20190042928A1

公开(公告)日：2019-02-07

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/063 ,  H03M7/30 ,  G11C5/06 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.