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    COMPUTE NEAR MEMORY WITH BACKEND MEMORY
    2.
    发明申请
    COMPUTE NEAR MEMORY WITH BACKEND MEMORY 审中-公开

    公开(公告)号：US20200279850A1

    公开(公告)日：2020-09-03

    申请号：US16827542

    申请日：2020-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

    IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

    Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

    CHANNEL STRUCTURES FOR THIN-FILM TRANSISTORS
    5.
    发明申请
    CHANNEL STRUCTURES FOR THIN-FILM TRANSISTORS 有权

    公开(公告)号：US20220238685A1

    公开(公告)日：2022-07-28

    申请号：US17724331

    申请日：2022-04-19

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Cory WEBER ,  Van H. LE ,  Sean MA

    IPC: H01L29/47 ,  H01L27/108 ,  H01L27/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

    FinFET TRANSISTOR BASED RESISTIVE RANDOM ACCESS MEMORY
    8.
    发明申请
    FinFET TRANSISTOR BASED RESISTIVE RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20200098826A1

    公开(公告)日：2020-03-26

    申请号：US16141025

    申请日：2018-09-25

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Gregory CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Raghavan KUMAR ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Huseyin SUMBUL ,  Ian A. YOUNG

    IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

    Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

    TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS
    9.
    发明申请
    TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS 审中-公开

    公开(公告)号：US20200006388A1

    公开(公告)日：2020-01-02

    申请号：US16024696

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Gilbert DEWEY ,  Patrick MORROW ,  Aaron LILAK ,  Willy RACHMADY ,  Anh PHAN ,  Ehren MANNEBACH ,  Hui Jae YOO ,  Abhishek SHARMA ,  Van H. LE ,  Cheng-Ying HUANG

    IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8258

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

    STACKED THIN FILM TRANSISTORS
    10.
    发明申请
    STACKED THIN FILM TRANSISTORS 审中-公开

    公开(公告)号：US20190393249A1

    公开(公告)日：2019-12-26

    申请号：US16016387

    申请日：2018-06-22

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Justin WEBER ,  Harold KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Patrick MORROW

    IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8256

    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

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