公开(公告)号：US20190303750A1

公开(公告)日：2019-10-03

申请号：US16443548

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Gregory K. CHEN ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/08

Abstract: Examples described herein relate to a neural network whose weights from a matrix are selected from a set of weights stored in a memory on-chip with a processing engine for generating multiply and carry operations. The number of weights in the set of weights stored in the memory can be less than a number of weights in the matrix thereby reducing an amount of memory used to store weights in a matrix. The weights in the memory can be generated in training using gradients from back propagation. Weights in the memory can be selected using a tabulation hash calculation on entries in a table.

公开(公告)号：US20200233923A1

公开(公告)日：2020-07-23

申请号：US16839013

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F17/16 ,  G06N3/063 ,  G11C8/08 ,  G11C7/12 ,  G11C7/10 ,  G06F9/30 ,  G11C11/56 ,  G11C11/418 ,  G11C11/419

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

公开(公告)号：US20200026498A1

公开(公告)日：2020-01-23

申请号：US16586648

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Raghavan KUMAR ,  Ram KRISHNAMURTHY

IPC: G06F7/544 ,  G06F7/498 ,  G06F17/16 ,  G06F9/30 ,  G06F12/02

Abstract: A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.

公开(公告)号：US20200019847A1

公开(公告)日：2020-01-16

申请号：US16583217

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram KRISHNAMURTHY ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Deepak Vinayak KADETOTAD

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

公开(公告)号：US20200019846A1

公开(公告)日：2020-01-16

申请号：US16583201

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram KRISHNAMURTHY ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/063 ,  G06F7/523 ,  G06F7/509 ,  G06F9/30 ,  G06F9/38

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

公开(公告)号：US20190042928A1

公开(公告)日：2019-02-07

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/063 ,  H03M7/30 ,  G11C5/06 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

公开(公告)号：US20220012581A1

公开(公告)日：2022-01-13

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20200279850A1

公开(公告)日：2020-09-03

申请号：US16827542

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US20200097807A1

公开(公告)日：2020-03-26

申请号：US16697616

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Ram KRISHNAMURTHY

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A compute near memory binary neural network accelerator with digital circuits that achieves energy efficiencies comparable to or surpassing a compute near memory binary neural network accelerator with analog circuits is provided. The compute near memory binary neural network accelerator with digital circuits is more process scalable, robust to process, voltage and temperature variations, and immune to circuit noise.

公开(公告)号：US20190102170A1

公开(公告)日：2019-04-04

申请号：US16146430

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC: G06F9/30 ,  G06F9/38 ,  G11C11/419 ,  G11C13/00

Abstract: A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.