公开(公告)号：US11062203B2

公开(公告)日：2021-07-13

申请号：US15394897

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/063 ,  G06N3/04

Abstract: In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.

公开(公告)号：US10440377B2

公开(公告)日：2019-10-08

申请号：US13649560

申请日：2012-10-11

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Ram K. Krishnamurthy

IPC: H04N11/02 ,  H04N19/43 ,  H04N19/567

Abstract: In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.

公开(公告)号：US10382019B2

公开(公告)日：2019-08-13

申请号：US15992052

申请日：2018-05-29

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Ram K. Krishnamurthy

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/00 ,  H03K19/20 ,  H03K3/037

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

公开(公告)号：US20190042909A1

公开(公告)日：2019-02-07

申请号：US15821123

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

公开(公告)号：US09985612B2

公开(公告)日：2018-05-29

申请号：US15246445

申请日：2016-08-24

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Ram K. Krishnamurthy

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/00 ,  H03K19/20

CPC classification number: H03K3/3562 ,  H03K3/0375 ,  H03K19/0002 ,  H03K19/20

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.

公开(公告)号：US09961019B2

公开(公告)日：2018-05-01

申请号：US14579729

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Yejoong Kim

IPC: H04L12/933

CPC classification number: H04L49/109 ,  H04L45/60 ,  H04L49/60

Abstract: A packet-switched reservation request to be associated with a first data stream is received. A communication mode is selected. The communication mode is to be either a circuit-switched mode or a packet-switched mode. At least a portion of the first data stream is communicated in accordance with the communication mode.

公开(公告)号：US09859876B1

公开(公告)日：2018-01-02

申请号：US15247713

申请日：2016-08-25

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

IPC: H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/3562 ,  H03K3/0372 ,  H03K3/35625

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

公开(公告)号：US09787571B2

公开(公告)日：2017-10-10

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/26 ,  H04L12/727 ,  H04L12/933 ,  H04L12/773 ,  G06F15/78

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

公开(公告)号：US09391617B2

公开(公告)日：2016-07-12

申请号：US13889849

申请日：2013-05-08

Applicant: Intel Corporation

Inventor： Sanu K. Mathew ,  Rachael J. Parker ,  Ram K. Krishnamurthy

IPC: H03K19/003

CPC classification number: H03K19/00369 ,  H03K19/00315

Abstract: An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.

Abstract translation: 被设计成用于断言多个可能的输出状态之一（每个具有相等的概率）的IC单元被实现为基于IC单元内的随机变化来断言多个输出状态中的预定的一个，例如随机过程变化。 IC单元阵列可配置为在上电时提供硬件嵌入式密钥，该特征是选择的IC单元的随机变化的组合，在制造之前和之后都能够防止篡改，并且能够耐老化，瞬时热噪声， 和环境变化，如电压和温度波动。 该密钥可以用作但不限于平台根密钥，高带宽数字内容保护（HDCP）密钥，增强型隐私标识（EPID）密钥和/或高级访问内​​容系统（AACS）密钥）。 还公开了基于IC电池的输出状态来测量IC电池的稳定性和应力硬化的技术。

公开(公告)号：US20160182393A1

公开(公告)日：2016-06-23

申请号：US14579303

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Aaron T. Stillmaker

IPC: H04L12/863 ,  H04L12/935 ,  H04L12/26 ,  H04L12/911

CPC classification number: H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

Abstract translation: 接收到第一分组交换预约请求。 根据尽力而为的通信方案，通过第一电路交换信道来传送与第一分组交换预约请求相关联的数据。 接收第二分组交换预约请求。 根据保证的吞吐量通信方案，通过第二电路交换信道来传送与第二分组交换预约请求相关联的数据。