公开(公告)号：US20180373516A1

公开(公告)日：2018-12-27

申请号：US15634464

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL

IPC: G06F9/45

Abstract: Techniques and apparatus for distributing code via a translation process are described. In one embodiment, for example, an apparatus may include at least one memory and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a source code element to be translated to a target code element, determine source code information for the source code element, provide a translation request corresponding to the source code to a translation service, receive the target code element from the translation service, and execute the target code element in place of the source code element. Other embodiments are described and claimed.

公开(公告)号：US20170272096A1

公开(公告)日：2017-09-21

申请号：US15479087

申请日：2017-04-04

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  SEAN M. GULLEY ,  GILBERT M. WOLRICH

IPC: H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  H03M7/30 ,  H03M7/46

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

公开(公告)号：US20170052784A1

公开(公告)日：2017-02-23

申请号：US15346655

申请日：2016-11-08

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  GILBERT M. WOLRICH

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F7/02 ,  G06F9/30036 ,  G06F2207/025 ,  G06K9/6201 ,  H03M7/3086

Abstract: A processor is described having an instruction execution pipeline having a functional unit to execute an instruction that compares vector elements against an input value. Each of the vector elements and the input value have a first respective section identifying a location within data and a second respective section having a byte sequence of the data. The functional unit has comparison circuitry to compare respective byte sequences of the input vector elements against the input value's byte sequence to identify a number of matching bytes for each comparison. The functional unit also has difference circuitry to determine respective distances between the input vector ‘s elements’ byte sequences and the input value's byte sequence within the data.

Abstract translation: 描述了具有指令执行流水线的处理器，其具有功能单元，以执行将矢量元素与输入值进行比较的指令。 矢量元素和输入值中的每一个具有识别数据内的位置的第一相应部分和具有数据的字节序列的第二相应部分。 功能单元具有比较电路，用于将输入向量元素的各个字节序列与输入值的字节序列进行比较，以识别每个比较的匹配字节数。 功能单元还具有差分电路，以确定输入向量元素的字节序列与数据内的输入值的字节序列之间的相应距离。

公开(公告)号：US20160380772A1

公开(公告)日：2016-12-29

申请号：US14751881

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JASON W. BRANDT

IPC: H04L9/32 ,  H04L29/06

CPC classification number: H04L9/3242 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/64 ,  G09C1/00 ,  H04L2209/04 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/16

Abstract: A processor of an aspect includes a decode unit to decode a keyed-hash message authentication code instruction. The keyed-hash message authentication code instruction is to indicate a message, to indicate at least one value that is to represent at least one of key information and key indication information, and to indicate a destination storage location. An execution unit is coupled with the decode unit. The execution unit, in response to the keyed-hash message authentication code instruction, is to store a message authentication code corresponding to the message in the destination storage location. The message authentication code is to be consistent with a keyed-hash message authentication code algorithm that is to use a cryptographic hash algorithm. The message authentication code is to be based on a cryptographic key associated with the at least one value. Other processors, methods, systems, and instructions are disclosed.

Abstract translation: 一方面的处理器包括用于对密钥散列消息认证码指令进行解码的解码单元。 密钥哈希消息认证码指令是指示消息，以指示至少一个值来表示密钥信息和密钥指示信息中的至少一个，并指示目的地存储位置。 执行单元与解码单元耦合。 执行单元响应于密钥散列消息认证码指令，将与该消息相对应的消息认证码存储在目的地存储位置中。 消息认证码与使用加密散列算法的密钥散列消息认证码算法一致。 消息认证码将基于与至少一个值相关联的加密密钥。 公开了其他处理器，方法，系统和指令。

公开(公告)号：US20160313993A1

公开(公告)日：2016-10-27

申请号：US15203610

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30 ,  H04L9/06 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US20160197720A1

公开(公告)日：2016-07-07

申请号：US14872556

申请日：2015-10-01

Applicant: Intel Corporation

Inventor： SHAY GUERON ,  WAJDI K FEGHALI ,  VINODH GOPAL ,  RAGHUNANDAN MAKARAM ,  MARTIN G DIXON ,  SRINIVAS CHENNUPATY ,  MICHAEL KOUNAVIS

IPC: H04L9/06 ,  G06F9/38 ,  G06F9/30

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20150280917A1

公开(公告)日：2015-10-01

申请号：US14228056

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  VINODH GOPAL ,  KIRK S. YAP ,  WAJDI K. FEGHALI

IPC: H04L9/32 ,  G06F12/08

CPC classification number: H04L9/3239 ,  G06F9/30007 ,  G06F12/0811 ,  G06F2212/283 ,  H04L9/0643 ,  H04L2209/125

Abstract: An apparatus and method are described for executing hash functions on a processor. For example, one embodiment of a processor comprises: a register set including a first storage location and a second storage location in which state variables for a hash function are to be stored; an execution unit to execute the hash function and to initially designate the first storage location as storing a first set of state values used for computing rounds of the hash function, and to initially designate a second storage location as storing a second set of state values also used for computing the rounds of the hash function; and the execution unit to execute a plurality of rounds of the hash function using the first and second sets of state data, wherein executing includes swapping the designations of the first storage location and second storage location such that the first storage location is designated to store the first set of state values for a first set of rounds and the second set of state values for a second set of rounds, and wherein the second storage location is designated to store the second set of state values for the first set of rounds and the first set of state values for the second set of rounds.

Abstract translation: 描述了用于在处理器上执行散列函数的装置和方法。 例如，处理器的一个实施例包括：包括第一存储位置和第二存储位置的寄存器集合，其中将要存储散列函数的状态变量; 执行单元，用于执行所述散列函数，并且初始地将所述第一存储位置指定为存储用于计算所述散列函数的四舍五入的第一组状态值，并且初始地将第二存储位置指定为存储第二组状态值 用于计算散列函数的轮次; 所述执行单元使用所述第一和第二状态数据集来执行所述散列函数的多个轮，其中执行包括交换所述第一存储位置和所述第二存储位置的指定，使得所述第一存储位置被指定为存储 第一组轮次的第一组状态值和第二组轮次的第二组状态值，并且其中第二存储位置被指定为存储第一组轮次的第二组状态值，并且第一组轮 第二组轮的状态值集合。