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    Secure elliptic curve cryptography instructions
    23.
    发明授权
    Secure elliptic curve cryptography instructions 有权

    公开(公告)号：US10270598B2

    公开(公告)日：2019-04-23

    申请号：US15248643

    申请日：2016-08-26

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal

    IPC: H04L9/30 ,  G06F7/72 ,  G06F21/72

    Abstract: A processor of an aspect includes a decode unit to decode an elliptic curve cryptography (ECC) point-multiplication with obfuscated input information instruction. The ECC point-multiplication with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for an ECC point-multiplication operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the ECC point-multiplication with obfuscated input information instruction, is to store an ECC point-multiplication result in a destination storage location that is to be indicated by the ECC point-multiplication with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.

    Method and apparatus for high performance compression and decompression
    24.
    发明授权
    Method and apparatus for high performance compression and decompression 有权

    公开(公告)号：US10270464B1

    公开(公告)日：2019-04-23

    申请号：US15941968

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： James Guilford ,  Kirk Yap ,  Vinodh Gopal ,  Daniel Cutter ,  Wajdi Feghali

    IPC: H03M7/30 ,  H03M7/40

    Abstract: An apparatus and method for performing efficient lossless compression. For example, one embodiment of an apparatus comprises: first compression circuitry to identify and replace one or more repeated bit strings from an input data stream with distances to the one or more repeated bit strings, the first compression circuitry to generate a first compressed data stream comprising literal-length data identifying a first instance of each repeated bit string and distance data comprising distances from the first instance to each repeated instance of the repeated bit string; second compression circuitry to perform sorting, tree generation, and length calculations for literal-length values and distance values of the first compressed data stream, the second compression circuitry comprising: variable length code mapping circuitry to map each literal-length value and distance value to a variable length code; header generation circuitry to generate a header for a final compressed bit stream using the length calculations; and a transcoder to substitute the variable length codes in place of the literal-length and distance values to generate a compressed bit stream body, wherein the transcoder operates in parallel with the header generation circuitry; and bit stream merge circuitry to combine the header with the compressed bit stream body to generate a final lossless compressed bitstream.

    Hardware apparatuses and methods for data decompression
    26.
    发明授权
    Hardware apparatuses and methods for data decompression 有权

    公开(公告)号：US10177782B2

    公开(公告)日：2019-01-08

    申请号：US14757854

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Sudhir K. Satpathy ,  James D. Guilford ,  Sanu K. Mathew ,  Vinodh Gopal ,  Vikram B. Suresh

    IPC: H03M7/30 ,  H03M7/40 ,  G06F9/38 ,  G06F9/46

    Abstract: Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.

    Secure modular exponentiation processors, methods, systems, and instructions
    29.
    发明授权
    Secure modular exponentiation processors, methods, systems, and instructions 有权

    公开(公告)号：US10089500B2

    公开(公告)日：2018-10-02

    申请号：US14866334

    申请日：2015-09-25

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  Gilbert M. Wolrich

    IPC: H04L29/00 ,  G06F21/72 ,  G06F9/30 ,  H04L9/08

    Abstract: A processor of an aspect includes a decode unit to decode a modular exponentiation with obfuscated input information instruction. The modular exponentiation with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for a modular exponentiation operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the modular exponentiation with obfuscated input information instruction, is to store a modular exponentiation result in a destination storage location that is to be indicated by the modular exponentiation with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.

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