利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.03 秒)

    Current driver with over-driving function in a semiconductor device
    21.
    发明授权
    Current driver with over-driving function in a semiconductor device 失效
    在半导体器件中具有过驱动功能的电流驱动器

    公开(公告)号：US07446577B2

    公开(公告)日：2008-11-04

    申请号：US11154870

    申请日：2005-06-16

    申请人： Jae Il Kim ,  Kang Seol Lee

    发明人： Jae Il Kim ,  Kang Seol Lee

    IPC分类号： H03B1/00

    CPC分类号： H03K17/302 ,  H03K17/145 ,  H03K17/223 ,  H03K17/693

    摘要： Disclosed is a controller for driving current of a semiconductor device having an over-driving function, the controller comprising: a load means supplied with an internal voltage; a plurality of switching means, each of which has a first terminal connected to an external voltage and a second terminal connected to the load means, wherein at least one of the plurality of switching means is selectively turned on/off according to an voltage level of the external voltage.

    摘要翻译： 公开了一种用于驱动具有过驱动功能的半导体器件的电流的控制器，该控制器包括：被提供内部电压的负载装置; 多个开关装置，每个开关装置具有连接到外部电压的第一端子和连接到所述负载装置的第二端子，其中，所述多个开关装置中的至少一个根据所述多个开关装置的电压电平选择性地导通/ 外部电压。

    Test circuit and method of semiconductor memory apparatus
    23.
    发明授权
    Test circuit and method of semiconductor memory apparatus 有权
    半导体存储器件的测试电路和方法

    公开(公告)号：US08867287B2

    公开(公告)日：2014-10-21

    申请号：US13586047

    申请日：2012-08-15

    申请人： Jin Youp Cha ,  Jae Il Kim

    发明人： Jin Youp Cha ,  Jae Il Kim

    IPC分类号： G11C29/00 ,  G11C29/44 ,  G11C29/40 ,  G11C29/12 ,  G11C29/14

    CPC分类号： G11C29/40 ,  G11C29/34 ,  G11C2029/2602

    摘要： A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

    摘要翻译： 一种半导体存储装置，包括测试电路，该测试电路被配置为通过在第一测试模式期间比较和压缩存储在存储体内的多个存储单元中的数据来产生压缩数据，并且被配置为将压缩数据作为测试数据输出到输入/输出 在第一测试模式期间通过一个所选择的全局线填充测试电路，并且测试电路被配置为在第二测试模式期间将压缩数据发送到多个全局线路，在第二测试模式期间组合加载在各个全局线路中的压缩数据 并且在第二测试模式期间将组合结果作为测试数据输出到输入/输出焊盘。

    TEMPERATURE-SENSITIVE POLYETHYLENE GLYCOL / POLYESTER BLOCK COPOLYMER IN WHICH BIOACTIVE FUNCTIONAL GROUP IS INTRODUCED INTO SIDE CHAIN THEREOF
    24.
    发明申请
    TEMPERATURE-SENSITIVE POLYETHYLENE GLYCOL / POLYESTER BLOCK COPOLYMER IN WHICH BIOACTIVE FUNCTIONAL GROUP IS INTRODUCED INTO SIDE CHAIN THEREOF 有权
    生物活性官能团的温度敏感性聚乙烯甘油酯/聚酯嵌段共聚物被引入到其中

    公开(公告)号：US20130331526A1

    公开(公告)日：2013-12-12

    申请号：US13983905

    申请日：2011-11-22

    申请人： Moon Suk Kim ,  Jae Il Kim

    发明人： Moon Suk Kim ,  Jae Il Kim

    IPC分类号： A61K47/34

    CPC分类号： A61K47/34 ,  A61K9/0024 ,  A61K47/593 ,  A61K47/60 ,  A61L31/06 ,  A61L31/14 ,  A61L31/145 ,  A61L31/16 ,  C08G63/664 ,  C08G63/912 ,  C08G2261/126 ,  C08L71/02 ,  C08L2205/05 ,  C08L67/00 ,  C08L67/04

    摘要： The present invention relates to preparation and application of a temperature-sensitive polyethylene glycol/polyester block copolymer having a bioactive functional group introduced into a side chain thereof. More specifically, it relates to a temperature-sensitive polyethylene glycol/polyester block copolymer including a lactide segment having a bioactive functional group introduced into a side chain thereof and a method for preparing same. The temperature-sensitive polyethylene glycol/polyester block copolymer according to the present invention having a bioactive functional group introduced into a side chain thereof can be widely used as a drug delivery system, a support for tissue engineering, an adhesion inhibitor, etc.

    摘要翻译： 本发明涉及引入其侧链的具有生物活性官能团的温度敏感性聚乙二醇/聚酯嵌段共聚物的制备和应用。 更具体地说，本发明涉及包含引入其侧链的生物活性官能团的丙交酯链段的温度敏感性聚乙二醇/聚酯嵌段共聚物及其制备方法。 具有引入其侧链的生物活性官能团的本发明的温度敏感性聚乙二醇/聚酯嵌段共聚物可广泛用作药物递送系统，组织工程用支持体，粘着抑制剂等。

    Semiconductor memory apparatus
    25.
    发明授权
    Semiconductor memory apparatus 有权
    半导体存储装置

    公开(公告)号：US08331171B2

    公开(公告)日：2012-12-11

    申请号：US12843673

    申请日：2010-07-26

    申请人： Jae Il Kim ,  Jong Chern Lee

    发明人： Jae Il Kim ,  Jong Chern Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C7/10

    摘要： A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

    摘要翻译： 半导体存储装置包括：第一数据输入/输出线，被配置为从第一存储体传输数据; 第二数据输入/输出线，被配置为从所述第一存储体发送所述数据; 第一数据输出部，被配置为基于输入/输出模式对准并输出通过第一数据输入/输出线传输的数据; 以及第二数据输出部分，被配置为基于输入/输出模式和地址信号对准并输出通过第一输入/输出线或第二数据输入/输出线传输的数据。

    Apparatus for controlling the temperature of a wafer located at a pre-alignment stage
    26.
    发明授权
    Apparatus for controlling the temperature of a wafer located at a pre-alignment stage 有权
    用于控制位于预对准阶段的晶片的温度的装置

    公开(公告)号：US06370793B1

    公开(公告)日：2002-04-16

    申请号：US09584551

    申请日：2000-06-01

    申请人： Hee Sun Chae ,  Jae Il Kim ,  Yo Han Ahn

    发明人： Hee Sun Chae ,  Jae Il Kim ,  Yo Han Ahn

    IPC分类号： B65G4907

    CPC分类号： H01L21/67109 ,  G03F7/7075 ,  G03F7/70875 ,  G03F9/7011 ,  H01L21/67248 ,  H01L21/681 ,  H01L21/682 ,  Y10S414/136

    摘要： Apparatus for controlling the temperature of a wafer in a wafer pre-alignment stage has an air injection member for injecting cooling air towards a chucked wafer and an air guide for guiding a predetermined amount of the injected air towards a portion of the wafer adjacent the edge sensor to compensate for a relatively high temperature condition existing at the region of the edge sensor due to the operation thereof. The air injection member is connected with an air supplier and includes an air injection head having a bottom plate through which a plurality of injection holes extend. The air guide is a flow rate controlling plate which is disposed within the air injection head. The air introduced received by the air injection head is guided towards the region of the edge sensor by the flow rate controlling plate. By maintaining the surface temperature of a wafer uniform in the wafer pre-alignment stage, semiconductor device defects otherwise caused by the physical thermal expansion of wafers can be markedly reduced.

    摘要翻译： 用于控制晶片预对准台中的晶片的温度的装置具有用于将冷却空气朝向夹持晶片注入的空气注入构件和用于将预定量的注入空气引导到邻近边缘的晶片的一部分的空气引导件 传感器以补偿由于其操作而存在于边缘传感器的区域处的相对高的温度条件。 空气喷射构件与空气供应器连接，并且包括具有底板的空气喷射头，多个喷射孔通过该底板延伸。 空气引导件是设置在空气喷射头内的流量控制板。 由空气喷射头引入的空气被流量控制板引导到边缘传感器的区域。 通过将晶片的表面温度维持在晶片预对准阶段的均匀性，可以显着降低晶片的物理热膨胀导致的半导体器件缺陷。

    SEMICONDUCTOR MEMORY APPARATUS
    27.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器

    公开(公告)号：US20110188324A1

    公开(公告)日：2011-08-04

    申请号：US12843673

    申请日：2010-07-26

    申请人： Jae Il Kim ,  Jong Chern Lee

    发明人： Jae Il Kim ,  Jong Chern Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C7/10

    摘要： A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

    摘要翻译： 半导体存储装置包括：第一数据输入/输出线，被配置为从第一存储体传输数据; 第二数据输入/输出线，被配置为从所述第一存储体发送所述数据; 第一数据输出部，被配置为基于输入/输出模式对准并输出通过第一数据输入/输出线传输的数据; 以及第二数据输出部分，被配置为基于输入/输出模式和地址信号对准并输出通过第一输入/输出线或第二数据输入/输出线传输的数据。

    Anti-fuse circuit
    30.
    发明授权
    Anti-fuse circuit 有权
    防熔丝电路

    公开(公告)号：US08749298B2

    公开(公告)日：2014-06-10

    申请号：US13585972

    申请日：2012-08-15

    申请人： Jin Youp Cha ,  Jae Il Kim

    发明人： Jin Youp Cha ,  Jae Il Kim

    IPC分类号： H01H37/76 ,  H01H85/00

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.

    摘要翻译： 反熔丝电路包括：反熔丝单元，其包括能够响应于破裂信号被编程的反熔丝，并且被配置为产生对应于反熔丝的状态的熔丝信号; 虚拟熔丝单元，其包括虚拟熔丝并且被配置为产生对应于所述虚拟熔丝的状态的虚拟熔丝信号; 以及阻挡单元，被配置为响应于所述虚拟熔丝信号的状态而将所述熔丝信号输出为熔丝输出信号。