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公开(公告)号：US08161263B2
公开(公告)日：2012-04-17
申请号：US12024239
申请日：2008-02-01
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译： 处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。 第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。 预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。 第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。 预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。
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22.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT VARY AN AMOUNT OF DATA RETRIEVED FROM MEMORY BASED UPON A HINT 失效数据处理系统，处理器和方法，从基于记忆的记忆中提取的数据量变化不大公开(公告)号：US20090198903A1
公开(公告)日：2009-08-06
申请号：US12024170
申请日：2008-02-01
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译： 在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。 响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。 响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。
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公开(公告)号：US08595443B2
公开(公告)日：2013-11-26
申请号：US12024163
申请日：2008-02-01
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译： 一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。 基于使用历史来选择由数据预取请求预取的数据量。 将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。
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公开(公告)号：US08209488B2
公开(公告)日：2012-06-26
申请号：US12024248
申请日：2008-02-01
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/1027 , G06F2212/6026
摘要： A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.
摘要翻译： 使用间接寻址的数据预取技术包括在到存储器的访问流中监视与阵列相关联的数据指针值。 该技术确定数据指针值中是否存在模式。 然后基于数据指针值中的预测模式，填充与各个阵列地址/数据指针对相对应的条目的预取表。 然后，基于预取表中的相应条目，预取（例如，从存储器或另一存储器）分别的数据块（例如，相应的高速缓存行）。
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25.发明授权公开(公告)号：US08161264B2
公开(公告)日：2012-04-17
申请号：US12024246
申请日：2008-02-01
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction.
摘要翻译： 使用间接寻址执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。 然后取出包含在第一存储器地址的存储器的第一数据块（例如，第一高速缓存行）中的内容。 然后将偏移量添加到第一存储器地址处的存储器的内容以提供第一偏移存储器地址。 然后基于第一偏移存储器地址确定第二存储器地址。 包括第二存储器地址上的数据的第二数据块（例如，第二高速缓存行）然后被取出（例如，从存储器或另一个存储器）。 数据预取指令可以由指令中的唯一操作代码（操作码），唯一扩展操作码或字段（包括一个或多个位）来指示。
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公开(公告)号：US20090198948A1
公开(公告)日：2009-08-06
申请号：US12024186
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory address. Finally, a data block (e.g., a cache line) including data at the second memory address is fetched (e.g., from the memory or another memory).
摘要翻译： 用于执行间接数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。 然后获取第一个存储器地址上的存储器的内容。 从第一存储器地址处的存储器的内容确定第二存储器地址。 最后，取出包括第二存储器地址上的数据的数据块（例如，高速缓存行）（例如，从存储器或另一个存储器）。
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公开(公告)号：US07996564B2
公开(公告)日：2011-08-09
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译： 分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器 由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。 在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。 本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问 数据中心为远程存储器的节点ID。
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公开(公告)号：US20100268788A1
公开(公告)日：2010-10-21
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F15/167 , G06F9/46 , G06F12/00 , G06F12/10
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译： 分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器 由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。 在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。 本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问 数据中心为远程存储器的节点ID。
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公开(公告)号：US08966219B2
公开(公告)日：2015-02-24
申请号：US11928125
申请日：2007-10-30
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译： 在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。 使用中间地址访问高速缓冲存储器。 响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。 使用实际地址访问系统内存。
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30.发明授权Read and write aware cache with a read portion and a write portion of a tag and status array 有权具有读取部分和标签和状态数组的写入部分的读写感知高速缓存公开(公告)号：US08843705B2
公开(公告)日：2014-09-23
申请号：US13572916
申请日：2012-08-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。
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