System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
    21.
    发明授权
    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene 失效
    系统级原位集成电介质蚀刻工艺特别适用于铜双镶嵌

    公开(公告)号:US06949203B2

    公开(公告)日:2005-09-27

    申请号:US10379439

    申请日:2003-03-03

    摘要: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the barrier layer is etched through to the feature to be contacted in the second chamber of the multichamber substrate processing system using a process that discourages polymer formation over the relatively smooth interior surface of the second chamber. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps. In some embodiments the interior surface of the first chamber has a roughness between 100 and 200 Ra and in other embodiments the roughness of the first chamber's interior surface is between 110 and 160 Ra.

    摘要翻译: 在具有第一和第二蚀刻室的多室衬底处理系统中执行的集成原位蚀刻工艺。 在一个实施例中,第一室包括已经被粗糙化至少100个的内表面,而第二室包括具有小于约32μm的粗糙度的内表面, / SUB>。 该方法包括在向下的方向上转移其上形成有图案的光致抗蚀剂掩模,电介质层,阻挡层和衬底中的特征的衬底,以接触第一室,其中介电层被刻蚀在鼓励聚合物的过程中 在室的粗糙内表面上形成。 然后在真空条件下将衬底从第一室转移到第二室,并且在第二室中暴露于诸如氧的反应性等离子体以剥离沉积在衬底上的光致抗蚀剂掩模。 在光致抗蚀剂掩模被剥离之后,通过阻止在第二室的相对光滑的内表面上聚合物形成的工艺,阻挡层被蚀刻到多室基板处理系统的第二室中以接触的特征。 所有三个蚀刻步骤都是在系统级原位工艺中进行的,因此基板不会在台阶之间暴露于环境中。 在一些实施例中,第一室的内表面具有在100和200之间的粗糙度,而在其它实施例中,第一室的内表面的粗糙度在110和160之间, SUB>。