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117 条记录 (耗时 0.06 秒)

    Emulation of abstracted DIMMS using abstracted DRAMS
    27.
    发明授权
    Emulation of abstracted DIMMS using abstracted DRAMS 有权
    使用抽象的DRAMS仿真抽象的DIMMS

    公开(公告)号：US08631193B2

    公开(公告)日：2014-01-14

    申请号：US13473827

    申请日：2012-05-17

    申请人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

    发明人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

    摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

    摘要翻译： 本发明的一个实施例提出了一种抽象存储器子系统，其包括抽象存储器，每个存储器子系统可被配置为将存储器相关特性呈现到存储器系统接口上。 该特性可以通过逻辑信号或协议交换在存储器系统接口上呈现，并且特征可以包括地址空间，协议，存储器类型，功率管理规则，多个流水线级中的任何一个或多个， 多个银行，映射到物理银行，多个等级，定时特征，地址解码选项，总线周转时间参数，附加信号断言，子秩，多个平面或其他存储器 - 相关特征 一些实施例包括智能寄存器装置和/或智能缓冲器装置。 所公开的子系统的一个优点是可以优化存储器性能，而不管底层存储器硬件设备使用的特定协议。

    Simulating a refresh operation latency
    28.
    发明授权
    Simulating a refresh operation latency 有权
    模拟刷新操作延迟

    公开(公告)号：US08601204B2

    公开(公告)日：2013-12-03

    申请号：US13181716

    申请日：2011-07-13

    申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

    发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component.

    摘要翻译： 存储器装置包括多个存储器电路，接口电路具有第一类型的一个或多个第一部件和不同于第一类型的第二类型的一个或多个第二部件，一个或多个第一部件和第二部件中的每一个都是电耦合的 到主机系统。 接口电路可操作以向主机系统呈现模拟存储器电路，其中模拟存储器电路与多个存储器电路中的至少一个存储器电路之间的至少一个方面存在差异。 至少一个方面包括与刷新操作等待时间相关的定时，其中多个存储器电路中的每个存储器电路电耦合到至少一个第一部件和至少一个第二部件。

    Refresh management of memory modules
    29.
    发明授权
    Refresh management of memory modules 有权
    刷新内存模块的管理

    公开(公告)号：US08566516B2

    公开(公告)日：2013-10-22

    申请号：US11929631

    申请日：2007-10-30

    申请人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

    发明人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

    IPC分类号： G06F13/12

    CPC分类号： G11C11/40615 ,  G06F13/1636 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

    摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices.

    摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时 基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出。