公开(公告)号：US4467444A

公开(公告)日：1984-08-21

申请号：US174490

申请日：1980-08-01

申请人： William J. Harmon, Jr. ,  John R. Mick

发明人： William J. Harmon, Jr. ,  John R. Mick

IPC分类号： G06F7/575 ,  G06F9/30 ,  G06F9/302 ,  G06F9/00

CPC分类号： G06F7/575 ,  G06F9/3001 ,  G06F9/30018

摘要： A processor, used in microcomputer systems for performing data processing functions, includes an arithmetic-logic unit having three operand inputs to provide the capability of executing, in addition to typical arithmetic and logic operations, complex three-operand instructions in a single clock (instruction) cycle.

摘要翻译： 用于执行数据处理功能的微处理器系统中的处理器包括具有三个操作数输入的算术逻辑单元，以提供除了典型的算术和逻辑运算之外，还可以在单​​个时钟（指令）中执行复合三运算指令 ）周期。

公开(公告)号：USRE40932E1

公开(公告)日：2009-10-06

申请号：US10285031

申请日：2002-10-31

申请人： Thomas Diede ,  John R. Mick

发明人： Thomas Diede ,  John R. Mick

IPC分类号： G06F12/04

CPC分类号： G11C15/04

摘要： A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal. The second match signal disables each row of the third CAM sub-array for which the corresponding row of either the first or second CAM sub-array did not show a match. This comparison process continues in sequence with the remaining keys and CAM sub-arrays. The row of the CAM array that shows a match over the most consecutive comparison operations contains the longest match for the input data value. If multiple rows match over the same number of comparison operations, a priority encoder determines which location has the highest priority.

摘要翻译： 提供CAM系统，用于确定CAM阵列中的哪个数据字与输入数据值呈现最长的连续，未屏蔽的匹配。 输入数据值被划分为不重叠的子场，从而创建一系列密钥，该序列的第一密钥包括输入数据值的最低有效位（LSB）或最高有效位（MSB）。 CAM阵列沿着列划分成与由一系列键定义的子场相对应的类似的一系列非重叠子阵列。 第一CAM子阵列将第一密钥与其存储的数据位值行进行比较以产生第一匹配信号。 第一匹配信号禁用第一CAM子阵列的相应行不显示匹配的第二CAM子阵列的每一行。 然后，第二CAM子阵列将第二键与其使能的行进行比较，以产生第二匹配信号。 第二匹配信号禁用第一CAM子阵列或第二CAM子阵列的相应行不显示匹配的第三CAM子阵列的每一行。 该比较过程与剩余的键和CAM子阵列依次继续。 在最连续比较操作中显示匹配的CAM阵列行包含输入数据值的最长匹配。 如果在相同数量的比较操作中多行匹配，则优先级编码器确定哪个位置具有最高优先级。

公开(公告)号：US06785188B2

公开(公告)日：2004-08-31

申请号：US10059899

申请日：2002-01-28

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G11C800

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C2207/2218

摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

摘要翻译： 存储器系统包括存储器，输入电路和逻辑电路。 输入电路被耦合以接收存储器地址，并且在写入操作期间将相应的写入数据写入到SRAM中。 逻辑电路使写入数据在写入操作之后立即在任何顺序读取操作期间存储在输入电路中，然后在随后的写入操作期间被读入存储器。 在读取操作期间，如果一个或多个读取操作的地址等于要写入到存储器中的数据的地址，则可以从存储器系统读出在写入存储器之前存储在写入数据存储寄存器中的数据 存储器，同时临时存储在写入数据存储寄存器中。 因此，系统不会经历“总线周转”停机时间，从而增加了系统的带宽。 系统可以在单管道模式或双管道模式下运行。

公开(公告)号：US06577520B1

公开(公告)日：2003-06-10

申请号：US10274659

申请日：2002-10-21

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G11C1500

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A content addressable memory with programmable priority weighting and low cost match detection is described. A CAM array provides match and no-match indications of an input data word to a weight array. The weight array generates a forced match with an assigned weight that is lower than those assigned to match and no-match indications received from the CAM array. The weight array determines a winning match among the received match indications and the forced match according to their assigned weights, and provides an indication of the winning match to an encoder. The encoder provides an address of the winning match, and a match detect output which is generated from the success or lack thereof of the forced match being determined the winning match.

摘要翻译： 描述了具有可编程优先权重和低成本匹配检测的内容可寻址存储器。 CAM阵列将输入数据字的匹配和不匹配指示提供给权重阵列。 权重阵列产生与分配给权重的强制匹配，分配的权重低于从CAM阵列接收到的匹配和不匹配指示。 权重阵列根据其分配的权重确定接收到的匹配指示和强制匹配之间的获胜匹配，并且向编码器提供获胜匹配的指示。 编码器提供获胜匹配的地址，并且从强制匹配的成功或缺乏产生的匹配检测输出被确定为获胜匹配。

公开(公告)号：US06567338B1

公开(公告)日：2003-05-20

申请号：US09625382

申请日：2000-07-25

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G11C800

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C2207/2218

摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

公开(公告)号：US5581564A

公开(公告)日：1996-12-03

申请号：US629285

申请日：1990-12-18

申请人： Michael J. Miller ,  John R. Mick

发明人： Michael J. Miller ,  John R. Mick

IPC分类号： G06F11/22 ,  G01R31/3185 ,  H04B17/00

CPC分类号： G01R31/318572

摘要： A diagnostic circuit of the present invention has serial command input and output pins separate from its serial data input and output pins. In one embodiment, the diagnostic circuit has one command register and one data register, the data register receiving serially an input signal and providing serially an output signal through an input pin and an output pin respectively. In another embodiment, the diagnostic circuit has one command register and multiple data registers. Each data register including a zero-length register, can be separately addressed. In yet another embodiment, multiple serial data input and output pins are provided together with multiple data registers.

摘要翻译： 本发明的诊断电路具有与其串行数据输入和输出引脚分开的串行命令输入和输出引脚。 在一个实施例中，诊断电路具有一个命令寄存器和一个数据寄存器，数据寄存器串行地接收输入信号，并分别通过输入引脚和输出引脚提供输出信号。 在另一个实施例中，诊断电路具有一个命令寄存器和多个数据寄存器。 每个包括零长度寄存器的数据寄存器都可以单独寻址。 在另一个实施例中，多个串行数据输入和输出引脚与多个数据寄存器一起提供。

公开(公告)号：US4931974A

公开(公告)日：1990-06-05

申请号：US304069

申请日：1989-01-30

申请人： Danh Le Ngoc ,  John R. Mick

发明人： Danh Le Ngoc ,  John R. Mick

IPC分类号： G06F7/00 ,  G06F7/57 ,  G06F17/10 ,  G06F17/14

CPC分类号： G06F7/57 ,  G06F17/142 ,  G06F2207/3884 ,  G06F7/49947

摘要： For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register ("A"), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and "delay" the parameter represented by the state of signals externally developed on a "DA" bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for "bit-reverse order" addressing; and a unit for "rounding off" certain results.

公开(公告)号：US4760517A

公开(公告)日：1988-07-26

申请号：US920716

申请日：1986-10-17

申请人： Michael J. Miller ,  Danh Le Ngoc ,  John R. Mick

发明人： Michael J. Miller ,  Danh Le Ngoc ,  John R. Mick

IPC分类号： G06F9/22 ,  G06F7/00 ,  G06F7/57 ,  G06F15/78 ,  G06F9/00

CPC分类号： G06F15/7896

摘要： The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.

摘要翻译： 配置七端口随机存取存储器（RAM）单元，漏斗移位器，掩码发生器，算术逻辑单元（ALU），合并逻辑单元，多个复用器和三个双向数据总线的组合 形成三十二位，可级联，可编程的位片，适用于执行复杂的操作，例如那些需要从存储器单元读取多个操作数的操作数，在漏斗移位器中旋转，由算术逻辑单元 ，合并到合并逻辑单元中，结果将在单个周期内写入存储器单元。

公开(公告)号：US4633417A

公开(公告)日：1986-12-30

申请号：US622691

申请日：1984-06-20

申请人： Darrell L. Wilburn ,  John R. Mick

发明人： Darrell L. Wilburn ,  John R. Mick

IPC分类号： G06F9/455 ,  G06G7/48 ,  G01R15/12

CPC分类号： G06F9/455

摘要： An emulator for non-fixed instruction set VLSI devices having a microprogrammable emulator controller which can be used with a variety of VLSI devices and provide in-circuit emulation for general VLSI technology with capabilities comparable to the in-channel emulation capabilities previously available for fixed instruction set MOS microprocessors. This includes a device specific emulator head which is controlled by the emulator controller to emulate a VLSI device in a target machine. The VLSI device to be emulated is removed from the target machine and a device plug of the emulator head is inserted into the target machine. The VLSI device is placed in a socket in the emulator head. The emulator controller monitors instructions sent from the target machine to the VLSI device and provides instructions to the VLSI device.

摘要翻译： 用于非固定指令集VLSI器件的仿真器，具有可编程仿真器控制器，可与各种VLSI器件一起使用，并为通用VLSI技术提供在线仿真，具有与以前可用于固定指令的通道内仿真功能相当的功能 设置MOS微处理器。 这包括由仿真器控制器控制以模拟目标机器中的VLSI设备的特定于设备的仿真器头。 要仿真的VLSI设备从目标机器中移除，并将仿真器头的设备插头插入到目标机器中。 VLSI设备放置在仿真器头中的插座中。 仿真器控制器监视从目标机器发送到VLSI设备的指令，并向VLSI设备提供指令。