公开(公告)号：US4782461A

公开(公告)日：1988-11-01

申请号：US623160

申请日：1984-06-21

申请人： John R. Mick ,  Darrell L. Wilburn ,  Michael J. Miller

发明人： John R. Mick ,  Darrell L. Wilburn ,  Michael J. Miller

IPC分类号： G06F11/22 ,  G06F11/32 ,  G06F11/34 ,  G06F11/36 ,  G06F9/00

CPC分类号： G06F11/3652 ,  G06F11/322 ,  G06F11/22 ,  G06F11/34

摘要： A logical grouping of facilities within a computer development system where said facilities include breakpoint control, trace control and memory, a plurality of VLSI emulators, a plurality of storage device emulators, a plurality of emulators for simulating program or microprogram storage, and may be selectively assigned to said grouping by a user. Said selectively assigned facilities are associated with a clock control and are used for the design, debugging and testing of computer systems.

摘要翻译： 计算机开发系统内的设备的逻辑分组，其中所述设施包括断点控制，跟踪控制和存储器，多个VLSI仿真器，多个存储设备仿真器，用于模拟程序或微程序存储的多个仿真器，并且可以是选择性地 被用户分配给所述分组。 所述选择性分配的设施与时钟控制相关联，并且用于计算机系统的设计，调试和测试。

公开(公告)号：US5331645A

公开(公告)日：1994-07-19

申请号：US54346

申请日：1993-04-26

申请人： Michael J. Miller ,  Andy P. Chan ,  Robert W. Stodieck ,  John R. Mick

发明人： Michael J. Miller ,  Andy P. Chan ,  Robert W. Stodieck ,  John R. Mick

IPC分类号： G06F11/10 ,  H03M13/19 ,  H03M13/00

CPC分类号： G06F11/1048 ,  H03M13/19

摘要： A pair of similar, 32-bit, error detection and correction devices, including a "lower 32-bit" device (210) and an "upper 32-bit" device (212) are configured as a 64-bit, error detection and correction system. When a (64-bit) word of data is being stored in memory, the lower 32-bit device (210) develops, on an inter-device bus (226), signals representing generation partial check bits. The upper 32-bit device (212) receives the partial check bits (226), and develops signals representing final check bits (236) for storage with the corresponding data word in memory (220 and 234). When a (64-bit) word of data is being retrieved from memory, from signals representing check bits retrieved from memory (222), the lower 32-bit device (210) generates on an inter-device bus (224), signals representing correction partial syndromes. From the correction partial syndromes (224), the upper 32-bit device (212) develops, on another inter-device bus (228), signals representing correction partial check bits; generates full syndromes; and corrects errors in the upper 32-bits of the corresponding retrieved data word (240). From the correction partial check bits (228) the lower 32-bit device (210) (also) generates full syndromes; and corrects errors in the corresponding lower 32-bits of the retrieved data word (230).

摘要翻译： 包括“低32位”设备（210）和“高32位”设备（212）的一对类似的32位错误检测和校正设备被配置为64位错误检测和 校正系统 当存储器中存储（64位）数据字时，下位32位器件（210）在器件间总线（226）上产生表示生成部分校验位的信号。 上部32位设备（212）接收部分校验位（226），并且产生表示用于与存储器（220和234）中的相应数据字存储的最终校验位（236）的信号。 当从存储器检索到（64位）数据字时，从表示从存储器（222）检索的校验位的信号中，下部32位器件（210）在器件间总线（224）上产生信号， 矫正部分综合征。 从校正部分综合征（224），上部32位装置（212）在另一个装置间总线（228）上形成表示校正部分校验位的信号; 产生完整的综合征; 并纠正对应检索的数据字（240）的高32位的错误。 从校正部分校验位（228），下部32位器件（210）（也）产生完整的校正子; 并纠正检索的数据字（230）的相应较低32位中的错误。

公开(公告)号：US5581564A

公开(公告)日：1996-12-03

申请号：US629285

申请日：1990-12-18

申请人： Michael J. Miller ,  John R. Mick

发明人： Michael J. Miller ,  John R. Mick

IPC分类号： G06F11/22 ,  G01R31/3185 ,  H04B17/00

CPC分类号： G01R31/318572

摘要： A diagnostic circuit of the present invention has serial command input and output pins separate from its serial data input and output pins. In one embodiment, the diagnostic circuit has one command register and one data register, the data register receiving serially an input signal and providing serially an output signal through an input pin and an output pin respectively. In another embodiment, the diagnostic circuit has one command register and multiple data registers. Each data register including a zero-length register, can be separately addressed. In yet another embodiment, multiple serial data input and output pins are provided together with multiple data registers.

摘要翻译： 本发明的诊断电路具有与其串行数据输入和输出引脚分开的串行命令输入和输出引脚。 在一个实施例中，诊断电路具有一个命令寄存器和一个数据寄存器，数据寄存器串行地接收输入信号，并分别通过输入引脚和输出引脚提供输出信号。 在另一个实施例中，诊断电路具有一个命令寄存器和多个数据寄存器。 每个包括零长度寄存器的数据寄存器都可以单独寻址。 在另一个实施例中，多个串行数据输入和输出引脚与多个数据寄存器一起提供。

公开(公告)号：US4760517A

公开(公告)日：1988-07-26

申请号：US920716

申请日：1986-10-17

申请人： Michael J. Miller ,  Danh Le Ngoc ,  John R. Mick

发明人： Michael J. Miller ,  Danh Le Ngoc ,  John R. Mick

IPC分类号： G06F9/22 ,  G06F7/00 ,  G06F7/57 ,  G06F15/78 ,  G06F9/00

CPC分类号： G06F15/7896

摘要： The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.

摘要翻译： 配置七端口随机存取存储器（RAM）单元，漏斗移位器，掩码发生器，算术逻辑单元（ALU），合并逻辑单元，多个复用器和三个双向数据总线的组合 形成三十二位，可级联，可编程的位片，适用于执行复杂的操作，例如那些需要从存储器单元读取多个操作数的操作数，在漏斗移位器中旋转，由算术逻辑单元 ，合并到合并逻辑单元中，结果将在单个周期内写入存储器单元。

公开(公告)号：US06470418B1

公开(公告)日：2002-10-22

申请号：US09232413

申请日：1999-01-15

申请人： Chuen-Der Lien ,  Chau-Chin Wu ,  John R. Mick

发明人： Chuen-Der Lien ,  Chau-Chin Wu ,  John R. Mick

IPC分类号： G06F1200

CPC分类号： G06F17/30982 ,  G11C7/1039 ,  G11C15/00

摘要： A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.

摘要翻译： 一种内容寻址存储器（CAM）系统，其包括分别产生具有较高和较低优先级的第一和第二组匹配控制信号的第一和第二CAM阵列。 第一个CAM阵列在第一个存储器周期中被使能，并且分析第一组匹配控制信号。 如果在第一CAM阵列中存在匹配，则使能第一优先级编码器来处理第一组匹配控制信号。 如果不存在匹配，则不启用第一优先级编码器，并且启动第二存储器周期。 第二个CAM阵列在第二个存储周期中被使能，第二组信号被分析。 如果在第二CAM阵列中存在匹配，则使能第二优先级编码器来处理第二组匹配控制信号。 如果不存在匹配，则不启用第二优先级编码器。

公开(公告)号：US06249480B1

公开(公告)日：2001-06-19

申请号：US09429849

申请日：1999-10-28

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G11C800

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C2207/2218

摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

摘要翻译： 存储器系统包括存储器，输入电路和逻辑电路。 输入电路被耦合以接收存储器地址，并且在写入操作期间将相应的写入数据写入到SRAM中。 逻辑电路使写入数据在写入操作之后立即在任何顺序读取操作期间存储在输入电路中，然后在随后的写入操作期间被读入存储器。 在读取操作期间，如果一个或多个读取操作的地址等于要写入到存储器中的数据的地址，则可以从存储器系统读出在写入存储器之前存储在写入数据存储寄存器中的数据 存储器，同时临时存储在写入数据存储寄存器中。 因此，系统不会经历“总线周转”停机时间，从而增加了系统的带宽。 系统可以在单管道模式或双管道模式下运行。

公开(公告)号：US6115320A

公开(公告)日：2000-09-05

申请号：US28206

申请日：1998-02-23

申请人： John R. Mick ,  Mark W. Baumann

发明人： John R. Mick ,  Mark W. Baumann

IPC分类号： G11C11/419 ,  G11C8/00

CPC分类号： G11C11/419

摘要： A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

摘要翻译： 提出了包括存储器阵列，输入电路和逻辑电路的存储器系统。 输入电路被耦合以接收数据字的每个字节的存储器地址和一组单独的写入控制。 在写入操作期间，输入电路还接收要写入SRAM的相应写入数据。 逻辑电路使得写入数据和写入控制信息在写入操作之后的任何顺序读取操作期间存储在输入电路中，然后在随后的写入操作期间被读取到存储器中。 在读取操作期间，如果一个或多个读取操作的地址等于要写入到存储器中的数据的地址，则可以从存储器系统读出在写入存储器之前存储在写入数据存储寄存器中的数据 存储器，同时临时存储在写入数据存储寄存器中。

公开(公告)号：US5838631A

公开(公告)日：1998-11-17

申请号：US635128

申请日：1996-04-19

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G11C7/10 ,  G11C13/00

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C2207/2218

摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

公开(公告)号：US6094399A

公开(公告)日：2000-07-25

申请号：US253577

申请日：1999-02-19

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G11C7/10 ,  G11C13/00

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C2207/2218

摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data is storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

摘要翻译： 存储器系统包括存储器，输入电路和逻辑电路。 输入电路被耦合以接收存储器地址，并且在写入操作期间将相应的写入数据写入到SRAM中。 逻辑电路使写入数据在写入操作之后立即在任何顺序读取操作期间存储在输入电路中，然后在随后的写入操作期间被读入存储器。 在读取操作期间，如果一个或多个读取操作的地址等于要写入的数据的地址，那么存储在写入数据中的数据是在被读入存储器之前的存储寄存器，可以从存储器系统读出 存储器暂时存储在写数据存储寄存器中。 因此，系统不会经历“总线周转”停机时间，从而增加了系统的带宽。 系统可以在单管道模式或双管道模式下运行。

公开(公告)号：US5920580A

公开(公告)日：1999-07-06

申请号：US615546

申请日：1996-03-11

申请人： John R. Mick

发明人： John R. Mick

IPC分类号： G06F11/10 ,  G11C29/00

CPC分类号： G06F11/1028

摘要： A multi-error detector uses single byte error correcting-double byte error detecting codes but detects some multiple errors including double, triple, quadruple and more errors in a code. To detect the multiple errors, the multi-error detectors uses error pointer and a syndrome which are generated by error correction circuitry. Multiple errors are indicated when the syndrome indicates an error and either none or more than one of the error pointers are set. In one embodiment, a tree of half adders has least significant output bits from the adders coupled to input terminals of subsequent adders in the tree. Circuit logic detects multiple errors from the least significant output bit of the last adder in the tree and the more significant output bits from all the adders.

摘要翻译： 多错误检测器使用单字节错误纠正双字节错误检测码，但是在代码中检测到一些多重错误，包括双重，三倍，四倍和更多错误。 为了检测多个错误，多重检测器使用由纠错电路产生的错误指针和综合征。 当错误指示一个错误，并且没有或多于一个错误指针被设置时，指示多个错误。 在一个实施例中，半加法器的树具有来自耦合到树中的后续加法器的输入端的加法器的最低有效输出比特。 电路逻辑从树中最后一个加法器的最低有效输出位检测多个错误，并从所有加法器检测到更高有效的输出位。