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    Phase lock loop system and method
    21.
    发明授权
    Phase lock loop system and method 失效
    锁相环系统及方法

    公开(公告)号：US06577174B2

    公开(公告)日：2003-06-10

    申请号：US09910999

    申请日：2001-07-23

    申请人： Kevin Wayne Locker ,  Joseph Murray

    发明人： Kevin Wayne Locker ,  Joseph Murray

    IPC分类号： H03L700

    CPC分类号： H03L7/07 ,  G06F1/12 ,  H04J3/0688

    摘要： Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.

    摘要翻译： 对称交叉耦合PLL电路在两个独立的时钟信号之间提供伪同步，特别适用于容错应用。 独立振荡器为每个PLL电路提供输入信号。 PLL电路包括分频电路，其在输入时钟信号的某些次倍提供输出信号。 来自交叉耦合PLL电路的输出时钟信号之间的相位关系由相位检测器电路监视。 如果一个输出时钟信号的相位被确定为相对于另一个输出时钟信号提前，则通过暂时增加产生相位超前信号的PLL电路的分频比来延迟该输出时钟信号的相位。

    Flexibly Integrating Endpoint Logic Into Varied Platforms
    24.
    发明申请
    Flexibly Integrating Endpoint Logic Into Varied Platforms 审中-公开
    将端点逻辑灵活集成到各种平台中

    公开(公告)号：US20140052889A1

    公开(公告)日：2014-02-20

    申请号：US13968504

    申请日：2013-08-16

    申请人： Michael Klinglesmith ,  Mohan Nair ,  Joseph Murray

    发明人： Michael Klinglesmith ,  Mohan Nair ,  Joseph Murray

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4027 ,  G06F13/105 ,  G06F13/4221 ,  G06F2213/0026 ,  H04L12/1845 ,  H04L12/40032 ,  H04L12/6418 ,  H04L29/08468 ,  H04L67/1078

    摘要： In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明涉及一种具有耦合在上游结构和集成设备结构之间的虚拟端口的集成端点，该虚拟端口包括多功能逻辑，以处理与一个或多个知识产权（IP） 集成设备结构。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。 描述和要求保护其他实施例。

    Compact laser sensors and monitoring systems including such sensors
    25.
    发明授权
    Compact laser sensors and monitoring systems including such sensors 失效
    紧凑型激光传感器和监控系统，包括这样的传感器

    公开(公告)号：US08520472B2

    公开(公告)日：2013-08-27

    申请号：US11917130

    申请日：2006-06-13

    申请人： Joseph Murray ,  Gregg Johnson

    发明人： Joseph Murray ,  Gregg Johnson

    IPC分类号： G01H9/00 ,  G01L1/24

    CPC分类号： G01V1/186 ,  G01D5/344

    摘要： Improved laser sensors (10) employing doped laser crystals (24) for transducing output proportional to forces impinging upon the sensors. The disclosed sensors are compact, low powered and may be constructed relatively inexpensively from readily available materials. The disclosed sensors eliminate the need for costly, optical power-sapping fiber connections at the laser crystals. According to certain embodiments, the disclosed sensors are configured for local recovery of output signals using conventional digital telemetry. According to other embodiments, the sensors generate output through a dense wavelength division multiplexing (DWDM) laser (28), thereby allowing remote recovery without the need for frequency division multiplexing and issues involved with preloading the sensors to produce beat frequencies in unique bands.

    摘要翻译： 改进的激光传感器（10）使用掺杂的激光晶体（24）来传导与撞击在传感器上的力成比例的输出。 所公开的传感器是紧凑的，低功率的，并且可以从容易获得的材料相对廉价地构造。 所公开的传感器消除了在激光晶体处需要昂贵的光功率光纤连接的需要。 根据某些实施例，所公开的传感器被配置为使用常规数字遥测来局部恢复输出信号。 根据其他实施例，传感器通过密集波分复用（DWDM）激光器（28）产生输出，从而允许远程恢复，而不需要频分复用，以及涉及预加载传感器以产生独特频带中的拍频的问题。

    METHOD AND APPARATUS FOR SENDING AN AGGREGATED BEACON
    27.
    发明申请
    METHOD AND APPARATUS FOR SENDING AN AGGREGATED BEACON 审中-公开
    用于发送聚集的信标的方法和装置

    公开(公告)号：US20120026941A1

    公开(公告)日：2012-02-02

    申请号：US13034472

    申请日：2011-02-24

    申请人： Saad Ahmad ,  Jean-Louis Gauvreau ,  Rocco DiGirolamo ,  Zinan Lin ,  Joseph Murray ,  Alexander Reznik ,  Alpaslan Demir ,  Angelo A. Cuffaro ,  Zaid Al-Khatib

    发明人： Saad Ahmad ,  Jean-Louis Gauvreau ,  Rocco DiGirolamo ,  Zinan Lin ,  Joseph Murray ,  Alexander Reznik ,  Alpaslan Demir ,  Angelo A. Cuffaro ,  Zaid Al-Khatib

    IPC分类号： H04W84/18

    CPC分类号： H04W48/16 ,  H04W16/14 ,  H04W48/12

    摘要： Techniques for sending an aggregated beacon in a cognitive wireless network are disclosed. A beacon device may segment beacon information and send beacon segments via a plurality of channels simultaneously. A certain information elements of the beacon information may be included in each beacon segment. Each beacon segment may include channel information for other beacon segments that are transmitted simultaneously. Alternatively, a discovery beacon may be transmitted in addition to a regular beacon. The discovery beacon may include information indicating an operating channel on which the regular beacon is transmitted. The discovery beacon may be transmitted using a predetermined channel bandwidth, with a smaller beacon interval than the regular beacon, or in a frequency hopping fashion. The discovery beacon may be sent on a channel selected based on a regulatory class and corresponding channel information. The discovery beacon may be transmitted on a side channel.

    摘要翻译： 公开了在认知无线网络中发送聚合信标的技术。 信标设备可以分段信标信息并经由多个信道同时发送信标段。 信标信息的某些信息元素可以被包括在每个信标段中。 每个信标段可以包括同时传输的其他信标段的信道信息。 或者，除了常规信标之外，可以发送发现信标。 发现信标可以包括指示发送常规信标的操作信道的信息。 可以使用具有比常规信标更小的信标间隔的预定信道带宽或以跳频方式来发送发现信标。 发现信标可以在基于监管类别和对应信道信息所选择的信道上发送。 发现信标可以在侧信道上发送。

    Serial signal ordering in serial general purpose input output (SGPIO)
    28.
    发明申请
    Serial signal ordering in serial general purpose input output (SGPIO) 审中-公开
    串行通用输入输出串行信号排序（SGPIO）

    公开(公告)号：US20070079032A1

    公开(公告)日：2007-04-05

    申请号：US11241161

    申请日：2005-09-30

    申请人： Sailesh Bissessur ,  Joseph Murray ,  Brian Skerry ,  Robert Sheffield ,  Richard Beckett ,  Gregory Tse

    发明人： Sailesh Bissessur ,  Joseph Murray ,  Brian Skerry ,  Robert Sheffield ,  Richard Beckett ,  Gregory Tse

    IPC分类号： G06F13/38

    CPC分类号： G06F13/4291

    摘要： An apparatus may include a Serial General Purpose Input Output (SGPIO) initiator device. The SGPIO initiator device may have terminals to receive parallel input signals. The device may also have parallel-to-serial conversion logic to convert the parallel input signals to a serial stream. The device may further have signal ordering logic. The signal ordering logic may be in communication with the terminals and may be in communication with the parallel-to-serial conversion logic. The signal ordering logic may determine an order in which the parallel input signals are provided in the serial stream. Methods of ordering signals within an SGPIO initiator device and systems having SGPIO initiator devices are also disclosed.

    摘要翻译： 设备可以包括串行通用输入输出（SGPIO）启动器设备。 SGPIO启动器设备可以具有用于接收并行输入信号的终端。 该器件还可具有并行到串行转换逻辑，以将并行输入信号转换为串行流。 该装置还可以具有信号排序逻辑。 信号排序逻辑可以与终端通信，并且可以与并行到串行转换逻辑通信。 信号排序逻辑可以确定在串行流中提供并行输入信号的顺序。 还公开了在SGPIO启动器设备和具有SGPIO启动器设备的系统中排序信号的方法。

    Data integrity processing and protection techniques
    29.
    发明申请
    Data integrity processing and protection techniques 审中-公开
    数据完整性处理和保护技术

    公开(公告)号：US20060136619A1

    公开(公告)日：2006-06-22

    申请号：US11017183

    申请日：2004-12-16

    申请人： Samantha Edirisooriya ,  Gregory Tse ,  Joseph Murray

    发明人： Samantha Edirisooriya ,  Gregory Tse ,  Joseph Murray

    IPC分类号： G06F5/00

    CPC分类号： G06F13/28

    摘要： Techniques to accelerate block guard processing of data by use of block guard units in a path between a source memory device and an originator of a data transfer request. The block guard unit may intercept the data transfer request and data transferred in response to the data transfer request. The block guard unit may utilize a cache to store information useful to verify block guards associated with the data.

    摘要翻译： 通过使用源存储器设备和数据传输请求的发起者之间的路径中的块保护单元来加速对数据的块保护处理的技术。 块保护单元可以拦截响应于数据传输请求传送的数据传输请求和数据。 块保护单元可以利用高速缓存来存储用于验证与数据相关联的块保护的有用信息。

    Integrated circuit capable of memory access control
    30.
    发明申请
    Integrated circuit capable of memory access control 审中-公开
    具有内存访问控制的集成电路

    公开(公告)号：US20060047934A1

    公开(公告)日：2006-03-02

    申请号：US10931278

    申请日：2004-08-31

    申请人： Mark Schmisseur ,  Joseph Murray ,  Richard Mackey ,  Micheil Lee

    发明人： Mark Schmisseur ,  Joseph Murray ,  Richard Mackey ,  Micheil Lee

    IPC分类号： G06F12/00

    CPC分类号： G06F13/12

    摘要： A method according to one embodiment may include selecting a port, among a plurality of ports. The method of this embodiment may also include selecting between a memory read request and a memory write request from at least one port, among the plurality of ports, based on, at least in part, at least one memory access rule. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    摘要翻译： 根据一个实施例的方法可以包括在多个端口之中选择端口。 该实施例的方法还可以包括至少部分地基于至少一个存储器访问规则来选择在多个端口中的至少一个端口的存储器读请求和存储器写请求之间。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。