摘要:
The present invention is a method and apparatus for regulating current consumption and output current of a charge pump. According to some embodiments of the present invention, a first current coming into the charge pump and a second current coming into a driver of at least one of one or more stages of the charge pump is measured. A control loop may regulate one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages.
摘要:
Measuring and controlling current consumption and output current of a charge pump by measuring a first current coming into the charge pump; and measuring a second current coming into a driver for at least one of the one or more stages of the charge pump. A control loop may one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages, or by decreasing the current consumption by adjusting a load connected to the output of the charge pump pipe. The first and second currents may be compared with first and second reference currents. A load connected to the charge pump may comprise non-volatile memory cells, and the charge pump may be implemented on a same integrated circuit chip as the memory cells.
摘要:
A method includes controlling the connection of a charge pump output to a load capacitor as a function of activation control signals to an oscillator controlling the charge pump. A charge pump system includes a charge pump, an oscillator, a switching element and an enable signal generator. The switching element connects and disconnects the charge pump from a load capacitor. The enable signal generator is connected to the oscillator and to the switching element and enables and disables the oscillator and the switching element as a function of the output of the charge pump.
摘要:
A method for measuring output current of a charge pump, the method including providing a charge pump including a plurality of n charge pump stages, wherein an output of stage n−1(Von−1) is output to stage n, an output voltage of stage n being referred to as charge pump voltage output Vout, connecting an additional output pass device to the output of stage n−1, an output voltage of the additional output pass device being referred to as Voutm, forcing Voutm to be at least approximately equal to Vout, drawing at least one of output voltage (Voutm) and output current (Ioutm) from the additional output pass device, measuring Ioutm (e.g., comparing Ioutm with a reference current), and correlating Iout with Ioutm.
摘要:
A delay device for delaying the activation of a sensing indication signal includes a reference word-line, a reference word-line driver, and a comparator. The reference word-line driver is controlled by a strobe signal, and is connected to the reference word-line and a reference word-line voltage. Additionally, when so indicated by the strobe signal, the reference word-line driver provides the reference word-line voltage to the reference word-line. The comparator is connected to the reference word-line and to the reference word-line voltage and activates the sensing indication signal when the voltage on the reference word-line is at least equal to a predetermined function of the reference word-line voltage.
摘要:
A method and apparatus for erasing a single floating gate transistor in an array of floating gate transistors is provided. A selected floating gate transistor, which is located in a first row and a first column of the array, is erased as follows. A low voltage V.sub.LOW (e.g., 0 Volts) is applied to the gate of each transistor in the first row of the array. An erase voltage V.sub.ERASE (e.g., 8 Volts) is applied to the drain of each transistor in the first column of the array. An intermediate voltage V.sub.INT (e.g., 3 Volts) is applied to the source of each transistor in the array, as well as to the drain of each transistor of the array that is not in the first column. Under these conditions, only the selected floating gate transistor is erased. Other floating gate transistors in the first column are not erased because the gate-to-drain voltages of these transistors are limited by the intermediate voltage V.sub.INT applied to their gates.