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1.发明授权Measuring and controlling current consumption and output current of charge pumps 有权测量和控制电荷泵的电流消耗和输出电流公开(公告)号：US07605579B2
公开(公告)日：2009-10-20
申请号：US11602222
申请日：2006-11-21
CPC分类号： H02M3/073 , H02M2001/0009
摘要： The present invention is a method and apparatus for regulating current consumption and output current of a charge pump. According to some embodiments of the present invention, a first current coming into the charge pump and a second current coming into a driver of at least one of one or more stages of the charge pump is measured. A control loop may regulate one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages.
摘要翻译： 本发明是用于调节电荷泵的电流消耗和输出电流的方法和装置。 根据本发明的一些实施例，测量进入电荷泵的第一电流和进入电荷泵的一个或多个级中的至少一个的驱动器的第二电流。 控制回路可以调节电荷泵的一个或多个参数和/或连接到电荷泵的负载，例如通过调节以下的一个或多个：电源电压; 舞台的电压; 舞台的频率和/或占空比; 和阶段数。
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2.发明申请Measuring and controlling current consumption and output current of charge pumps 有权测量和控制电荷泵的电流消耗和输出电流公开(公告)号：US20080094127A1
公开(公告)日：2008-04-24
申请号：US11602222
申请日：2006-11-21
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2001/0009
摘要： Measuring and controlling current consumption and output current of a charge pump by measuring a first current coming into the charge pump; and measuring a second current coming into a driver for at least one of the one or more stages of the charge pump. A control loop may one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages, or by decreasing the current consumption by adjusting a load connected to the output of the charge pump pipe. The first and second currents may be compared with first and second reference currents. A load connected to the charge pump may comprise non-volatile memory cells, and the charge pump may be implemented on a same integrated circuit chip as the memory cells.
摘要翻译： 通过测量进入电荷泵的第一电流来测量和控制电荷泵的电流消耗和输出电流; 以及测量进入所述电荷泵的所述一个或多个阶段中的至少一个的驱动器的第二电流。 控制回路可以是电荷泵的一个或多个参数和/或连接到电荷泵的负载，例如通过调节以下的一个或多个：电源电压; 舞台的电压; 舞台的频率和/或占空比; 或通过调节连接到电荷泵管的输出的负载来减小电流消耗。 可以将第一和第二电流与第一和第二参考电流进行比较。 连接到电荷泵的负载可以包括非易失性存储器单元，并且电荷泵可以在与存储器单元相同的集成电路芯片上实现。
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公开(公告)号：US20120063238A1
公开(公告)日：2012-03-15
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。
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公开(公告)号：US07532529B2
公开(公告)日：2009-05-12
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译： 一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考 模拟电压Vcomp以产生输出数字信号。 还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。 还公开了相关装置。
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公开(公告)号：US08098525B2
公开(公告)日：2012-01-17
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。
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公开(公告)号：US20090073774A1
公开(公告)日：2009-03-19
申请号：US12232437
申请日：2008-09-17
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 可以根据每个地址的预定义表来选择预充电的全局位线。 可以根据在下一个读取周期期间这些全局位线是否会干扰管道来完成全局位线的选择。
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公开(公告)号：US20060285402A1
公开(公告)日：2006-12-21
申请号：US11464253
申请日：2006-08-14
申请人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
发明人： Oleg Dadashev , Yoram Betser , Eduardo Maayan
IPC分类号： G11C5/14
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.
摘要翻译： 一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考 模拟电压Vcomp以产生输出数字信号。 还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。 还公开了相关装置。
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公开(公告)号：US08593881B2
公开(公告)日：2013-11-26
申请号：US13301826
申请日：2011-11-22
申请人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
发明人： Yaal Horesh , Oleg Dadashev , Yoram Betser , Avri Harush
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C7/12 , G11C7/18 , G11C16/26
摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.
摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。
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公开(公告)号：US06469929B1
公开(公告)日：2002-10-22
申请号：US09935013
申请日：2001-08-21
IPC分类号： G11C1604
摘要： A method for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to a memory cell. This dual clamping configuration/operation ensures a quick charge of the bit line while eliminating overcharging of the bit line. Thus, sensing the state of the memory cell is substantially independent of the size of the memory array. A sensing system for sensing the state of a memory cell can include a system bit line coupled to a terminal of the memory cell, a charge initiation device for activating a charge operation on the system bit line, and a control unit connected between the system bit line and the charge initiation device. The control unit includes a static clamp to charge the system bit line to a first predetermined voltage and a dynamic clamp to charge the system bit line to a second predetermined voltage.
摘要翻译： 用于感测存储器单元的状态的方法包括耦合到存储器单元的位线的动态和静态钳位。 这种双钳位配置/操作确保了位线的快速充电，同时消除了位线的过充电。 因此，感测存储器单元的状态基本上与存储器阵列的大小无关。 用于感测存储器单元的状态的感测系统可以包括耦合到存储器单元的端子的系统位线，用于激活系统位线上的充电操作的充电启动装置，以及连接在系统位之间的控制单元 线和充电引发装置。 控制单元包括用于将系统位线充电到第一预定电压的静态钳位电路和用于将系统位线充电到第二预定电压的动态钳位电路。
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公开(公告)号：US07202654B1
公开(公告)日：2007-04-10
申请号：US11236359
申请日：2005-09-27
IPC分类号： G05F3/16
CPC分类号： G05F3/262
摘要： A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . . Tn, wherein the transistor T1 is connected to a node n0, to which is connected another transistor T0 that receives an input bias voltage Vbias, and wherein a feedback voltage fb from node n0 is fed to an input of the differential amplifier, the differential amplifier receiving an input reference voltage Vref at one of its other inputs, and is also connected to positive voltage supply Vdd, the differential amplifier outputting to an NMOS transistor M, and wherein the high voltage regulator has a large diode stack gain and lower GDA*GNMOS*m, resulting in a generally constant feedback (loop) gain Gloop, wherein the loop gain is given by: Loop Gain=Gloop=Gstack*GDA*GNMOS*m wherein m is the ratio of the two currents I1 and I2, that is, I2=mI1, Gstack is the gain of the diode stack, GDA is the gain of the differential amplifier and GNMOS is the gain of the NMOS transistor M.
摘要翻译： 一种高电压调节器，包括包括一对晶体管的电流镜，其中一个晶体管连接到输出输出电压V OUT的节点;二极管叠层，包括多个串联连接的晶体管T T 1，T 2，...，N 2， 。 。 其中晶体管T 1连接到与另一个晶体管T 0连接的节点n 0 0 < SUB>接收输入偏置电压V SUB偏置，并且其中来自节点n0的反馈电压fb被馈送到差分放大器的输入端，差分放大器接收 输入参考电压V SUB参考电压，并且还连接到正电压源Vdd，该差分放大器输出到NMOS晶体管M，并且其中高压调节器具有大的二极管叠层 增益和更低的G N N N * N，导致大体上恒定的反馈（环路）增益G ，其中环路增益为 给了
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