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    Apparatus for generating write data and readout data
    23.
    发明授权
    Apparatus for generating write data and readout data 有权
    用于产生写入数据和读出数据的装置

    公开(公告)号：US08937844B2

    公开(公告)日：2015-01-20

    申请号：US13406945

    申请日：2012-02-28

    申请人： Shigehiro Asano ,  Toshikatsu Hida

    发明人： Shigehiro Asano ,  Toshikatsu Hida

    IPC分类号： G11C29/00 ,  G11C11/34 ,  G11C7/10 ,  G11C29/44

    CPC分类号： G11C7/1036 ,  G11C29/848 ,  G11C2029/4402

    摘要： An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.

    摘要翻译： 根据实施例的装置包括第一存储器，第二存储器，输入单元，位移号确定单元和输出单元。 第一存储器在识别信息和缺陷信息相关联的同时存储扇区的识别信息和指示数据线上存在缺陷的缺陷信息。 第二存储器具有大于第一数量的存储区域。 输入单元一次以第一个数字将数据输入到第二个存储器。 换档号确定单元确定换档号码。 输出单元根据缺陷信息将存储在头部存储区域之后的存储区域中的数据输出到基于缺陷信息的数据被提供给没有缺陷扇区的数据，并输出不同于 数据到有缺陷的数据线。

    DATA GENERATION APPARATUS
    24.
    发明申请
    DATA GENERATION APPARATUS 有权
    数据生成装置

    公开(公告)号：US20130077419A1

    公开(公告)日：2013-03-28

    申请号：US13406945

    申请日：2012-02-28

    申请人： Shigehiro Asano ,  Toshikatsu Hida

    发明人： Shigehiro Asano ,  Toshikatsu Hida

    IPC分类号： G11C29/00

    CPC分类号： G11C7/1036 ,  G11C29/848 ,  G11C2029/4402

    摘要： An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.

    摘要翻译： 根据实施例的装置包括第一存储器，第二存储器，输入单元，位移号确定单元和输出单元。 第一存储器在识别信息和缺陷信息相关联的同时存储扇区的识别信息和指示数据线上存在缺陷的缺陷信息。 第二存储器具有大于第一数量的存储区域。 输入单元一次以第一个数字将数据输入到第二个存储器。 换档号确定单元确定换档号码。 输出单元根据缺陷信息将存储在头部存储区域之后的存储区域中的数据输出到基于缺陷信息的数据被提供给没有缺陷扇区的数据，并输出不同于 数据到有缺陷的数据线。

    APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TASK MANAGEMENT
    25.
    发明申请
    APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TASK MANAGEMENT 审中-公开
    用于任务管理的设备，方法和计算机程序产品

    公开(公告)号：US20090019450A1

    公开(公告)日：2009-01-15

    申请号：US12041325

    申请日：2008-03-03

    申请人： Tatsuya MORI ,  Hidenori Matsuzaki ,  Shigehiro Asano

    发明人： Tatsuya MORI ,  Hidenori Matsuzaki ,  Shigehiro Asano

    IPC分类号： G06F9/46

    CPC分类号： G06F9/5033 ,  G06F9/5038 ,  G06F2209/5021 ,  G06F2209/506

    摘要： A task management apparatus comprises a plurality of processors, and correspondingly stores, a plurality of tasks to be assigned to the processors within a predetermined period of time, and temporal groups each of which is assigned to the plurality of the tasks. The task management apparatus assigns one of the tasks to one of the processors. After having assigned the task, the task management apparatus assigns, to the one of the processors that has finished processing the assigned task, the other tasks that are in correspondence with the same temporal group as the temporal group with which the assigned task is in correspondence, before assigning the tasks that are not in correspondence with the temporal group.

    摘要翻译： 任务管理装置包括多个处理器，并且相应地在预定时间段内存储要分配给处理器的多个任务，以及每个分配给多个任务的时间组。 任务管理装置将其中一个任务分配给一个处理器。 在分配了任务之后，任务管理装置向已经完成处理分配的任务的处理器之一分配与分配的任务相对应的与时间组相同的时间组的其他任务 在分配不与时间组对应的任务之前。

    Multiprocessor system
    26.
    发明申请
    Multiprocessor system 审中-公开
    多处理器系统

    公开(公告)号：US20080077928A1

    公开(公告)日：2008-03-27

    申请号：US11898881

    申请日：2007-09-17

    申请人： Hidenori Matsuzaki ,  Shigehiro Asano ,  Atsushi Shono

    发明人： Hidenori Matsuzaki ,  Shigehiro Asano ,  Atsushi Shono

    IPC分类号： G06F9/50

    CPC分类号： G06F9/5044

    摘要： A multiprocessor system includes a processor unit including a core A including a first processing mechanism for improving processing performance of data processing and a PM unit for collecting usage information of hardware resources being used or used in data processing and a core B having a second processing mechanism adopting the same processing system as the first processing mechanism and being inferior in processing performance to the first processing mechanism; and a scheduler for supplying a task not previously executed to the core A and a task to be re-executed to one of processor cores (A and B) to process the task, selected out of the processor unit by referencing the usage information of the hardware resources of the task previously collected in the PM unit at the execution time of application software including a plurality of tasks containing the same task.

    摘要翻译： 多处理器系统包括：处理器单元，其包括：核心A，其包括用于提高数据处理的处理性能的第一处理机构;以及用于收集在数据处理中使用或使用的硬件资源的使用信息的PM单元;以及具有第二处理机构 采用与第一处理机构相同的处理系统，并且处理性能劣于第一处理机构; 以及调度器，用于将先前未被执行的任务提供给核心A，以及将待执行的任务重新执行到处理器核心（A和B）中的一个，以处理从处理器单元中选出的任务，方法是参考 在应用软件的执行时间先前在PM单元中收集的任务的硬件资源包括包含相同任务的多个任务。

    Order-relation analyzing apparatus, method, and computer program product thereof
    27.
    发明授权
    Order-relation analyzing apparatus, method, and computer program product thereof 有权
    订单关系分析装置，方法及其计算机程序产品

    公开(公告)号：US08296769B2

    公开(公告)日：2012-10-23

    申请号：US12050685

    申请日：2008-03-18

    申请人： Hidenori Matsuzaki ,  Tatsuya Mori ,  Shigehiro Asano

    发明人： Hidenori Matsuzaki ,  Tatsuya Mori ,  Shigehiro Asano

    IPC分类号： G06F9/46

    CPC分类号： G06F11/3604

    摘要： An order-relation analyzing apparatus collects assigned destination processor information, a synchronization process order and synchronization information, determines a corresponding element associated with a program among a plurality of elements indicating an ordinal value of the program based on the assigned destination processor information, when an execution of the program is started, and calculates the ordinal value indicated by the corresponding element for each segment based on the synchronization information, when the synchronization process occurs while executing the program. When a first corresponding element associated with a second program, of which the execution starts after the execution of a first program associated with the first corresponding element finishes, is determined, the ordinal value of the second program is calculated by calculating the ordinal value indicated by the first corresponding element.

    摘要翻译： 订单关系分析装置收集分配的目的地处理器信息，同步处理顺序和同步信息，在基于分配的目的地处理器信息指示程序的序数值的多个元素中确定与程序相关联的对应元素，当 开始程序的执行，并且当执行程序时发生同步处理时，基于同步信息计算由每个段的相应元素指示的序数值。 当与执行与第一对应元件相关联的第一程序的执行开始的第二程序相关联的第一对应元件被确定时，通过计算第二程序的序数值来计算第二程序的顺序值， 第一个对应的元素。

    ORDER-RELATION ANALYZING APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT THEREOF
    28.
    发明申请
    ORDER-RELATION ANALYZING APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT THEREOF 有权
    订单关系分析设备，方法和计算机程序产品

    公开(公告)号：US20090019451A1

    公开(公告)日：2009-01-15

    申请号：US12050685

    申请日：2008-03-18

    申请人： Hidenori Matsuzaki ,  Tatsuya Mori ,  Shigehiro Asano

    发明人： Hidenori Matsuzaki ,  Tatsuya Mori ,  Shigehiro Asano

    IPC分类号： G06F9/46

    CPC分类号： G06F11/3604

    摘要： An order-relation analyzing apparatus collects assigned destination processor information, a synchronization process order and synchronization information, determines a corresponding element associated with a program among a plurality of elements indicating an ordinal value of the program based on the assigned destination processor information, when an execution of the program is started, and calculates the ordinal value indicated by the corresponding element for each segment based on the synchronization information, when the synchronization process occurs while executing the program. When a first corresponding element associated with a second program, of which the execution starts after the execution of a first program associated with the first corresponding element finishes, is determined, the ordinal value of the second program is calculated by calculating the ordinal value indicated by the first corresponding element.

    摘要翻译： 订单关系分析装置收集分配的目的地处理器信息，同步处理顺序和同步信息，在基于分配的目的地处理器信息指示程序的序数值的多个元素中确定与程序相关联的对应元素，当 开始程序的执行，并且当执行程序时发生同步处理时，基于同步信息计算由每个段的相应元素指示的序数值。 当与执行与第一对应元件相关联的第一程序的执行开始的第二程序相关联的第一对应元件被确定时，通过计算第二程序的序数值来计算第二程序的顺序值， 第一个对应的元素。

    Memory system and computer program product
    29.
    发明授权
    Memory system and computer program product 有权
    内存系统和计算机程序产品

    公开(公告)号：US08812774B2

    公开(公告)日：2014-08-19

    申请号：US13217461

    申请日：2011-08-25

    申请人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

    发明人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F11/1068

    摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.

    摘要翻译： 根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子 接收单元; 发电机组; 第二个表 和书写单位。 第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。 生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。 在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。 当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

    Semiconductor memory device and controlling method
    30.
    发明授权
    Semiconductor memory device and controlling method 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08612824B2

    公开(公告)日：2013-12-17

    申请号：US13038804

    申请日：2011-03-02

    申请人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

    发明人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

    IPC分类号： H03M13/00 ,  G11C29/00

    CPC分类号： G11C16/3418 ,  G11C16/00 ,  G11C29/028

    摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.

    摘要翻译： 半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。