公开(公告)号：US20160372353A1

公开(公告)日：2016-12-22

申请号：US15135022

申请日：2016-04-21

Applicant: KLA-Tencor Corporation

Inventor： Pradeep Vukkadala ,  Sathish Veeraraghavan ,  Jaydeep K. Sinha

IPC: H01L21/67 ,  G01B11/27 ,  G01B11/24 ,  G01B9/02 ,  G01B11/16

CPC classification number: H01L21/67288 ,  G01B9/02021 ,  G01B9/02027 ,  G01B9/02057 ,  G01B11/161 ,  G01B11/2441 ,  G01B11/272 ,  G03F7/70633 ,  G03F7/70783 ,  H01L21/67271 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.

Abstract translation: 本发明可以包括在第一和第二处理水平的晶片表面的多个点处获取晶片形状值，在每个点产生晶片形状变化值，在每个点产生一组形状变化值的斜率 使用所生成的形状变化值的斜率来计算一组处理工具可校正性，通过使用该集合计算每个点处的形状变化残差值的斜率，生成一组斜率变化残差（SSCR） 定义过程表面上分布的多个度量分析区域，然后基于每个度量分析区域内的一个或多个SSCR，为每个度量分析区域生成一个或多个残留斜率形状变化度量。

公开(公告)号：US20160062252A1

公开(公告)日：2016-03-03

申请号：US14597062

申请日：2015-01-14

Applicant: KLA-Tencor Corporation

Inventor： Sathish Veeraraghavan ,  Chin-Chou Huang

IPC: G03F9/00 ,  H01L21/68 ,  H01L21/67 ,  G03F7/20

CPC classification number: G03F7/70625 ,  G03F7/705 ,  G03F7/70633 ,  G03F7/70783

Abstract: Systems and methods for providing improved measurements and predictions of geometry induced overlay errors are disclosed. Information regarding variations of overlay errors is obtained and analyzed to improve semiconductor processes as well as lithography patterning. In some embodiments, a cascading analysis process is utilized to breakdown the wafer geometry induced overlay into various components. The breakdown analysis may also be utilized to determine effectiveness factors for the various components, which in turn may improve the prediction accuracy of the impact of wafer geometry on wafer overlay. Furthermore, the measurements and/or predictions of the wafer geometry induced overlay errors may be utilized to provide overlay monitoring and correction solutions.

Abstract translation: 公开了用于提供改进的测量和预测几何感应覆盖误差的系统和方法。 获得并分析关于覆盖误差变化的信息以改进半导体工艺以及光刻图案。 在一些实施例中，利用级联分析过程将晶片几何感应覆盖层分解成各种组件。 击穿分析还可以用于确定各种组件的有效性因素，这又可以提高晶片几何对晶片覆盖层的影响的预测精度。 此外，可以利用晶片几何引起的覆盖误差的测量和/或预测来提供覆盖监视和校正解决方案。

公开(公告)号：US20140114597A1

公开(公告)日：2014-04-24

申请号：US13656143

申请日：2012-10-19

Applicant: KLA-Tencor Corporation

Inventor： Haiguang Chen ,  Jaydeep Sinha ,  Sergey Kamensky ,  Sathish Veeraraghavan ,  Pradeep Vukkadala

IPC: G01B11/24 ,  G06F17/00

CPC classification number: G01B11/24 ,  G01B2210/56 ,  G01N21/9501 ,  G06F17/00 ,  H01L22/12

Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

Abstract translation: 公开了用于改善晶片高阶形状（HOS）表征和晶片分类的结果的系统和方法。 根据本公开的系统和方法基于局部形状。 将晶片图划分成多个测量点，以提高晶片形状表示的完整性。 可以针对晶片表征和/或分类目的计算各种基于站点的HOS度量值，并且还可以用作下游应用的控制输入。 此外，还提供了极坐标分割方案。 可以利用这种极性栅格划分方案将晶片表面划分成具有均匀位置区域的测量位置，同时提供良好的晶片边缘区域覆盖。