System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking
    5.
    发明申请
    System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking 有权
    基于半导体晶片卡盘的有限元模型预测面内失真的系统和方法

    公开(公告)号:US20160283625A1

    公开(公告)日:2016-09-29

    申请号:US15172667

    申请日:2016-06-03

    CPC classification number: G06F17/5018 H01L21/67288

    Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

    Abstract translation: 公开了用于预测半导体晶片夹持工艺中的晶片形状的面内失真(IPD)的系统和方法。 根据本公开的一个实施例,利用基于IPD预测的非线性有限元(FE)接触力学模型的一系列Zernike基晶片形状处理。 基于模拟的基于有限元模型的预测过程基本上更有效,并且提供了与使用全尺寸3-D晶片和卡盘几何信息的基于有限元模型的基于有限元模型的预测相当的精度,并且需要计算密集模拟。 此外,还公开了基于一系列Zernike基晶片形状图像的增强型HOS IPD / OPD预测处理。

    System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
    6.
    发明授权
    System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking 有权
    系统和方法来模拟基于半导体晶片夹持的面内失真预测的有限元模型

    公开(公告)号:US09430593B2

    公开(公告)日:2016-08-30

    申请号:US13735737

    申请日:2013-01-07

    CPC classification number: G06F17/5018 H01L21/67288

    Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

    Abstract translation: 公开了用于预测半导体晶片夹持工艺中的晶片形状的面内失真(IPD)的系统和方法。 根据本公开的一个实施例,利用仿真基于IPD预测的非线性有限元(FE)接触力学模型的过程。 基于模拟的基于有限元模型的预测过程基本上更有效,并且提供了与使用全尺寸3-D晶片和卡盘几何信息的基于有限元模型的基于有限元模型的预测相当的精度,并且需要计算密集模拟。 此外,还公开了基于一系列Zernike基晶片形状图像的增强型HOS IPD / OPD预测处理。

    Detection of selected defects in relatively noisy inspection data
    7.
    发明授权
    Detection of selected defects in relatively noisy inspection data 有权
    检测相对嘈杂的检查数据中选定的缺陷

    公开(公告)号:US09355440B1

    公开(公告)日:2016-05-31

    申请号:US13649080

    申请日:2012-10-10

    Abstract: Methods and systems for detection of selected defects in relatively noisy inspection data are provided. One method includes applying a spatial filter algorithm to inspection data acquired across an area on a substrate to determine a first portion of the inspection data that has a higher probability of being a selected type of defect than a second portion of the inspection data. The selected type of defect includes a non-point defect. The inspection data is generated by combining two or more raw inspection data corresponding to substantially the same locations on the substrate. The method also includes generating a two-dimensional map illustrating the first portion of the inspection data. The method further includes searching the two-dimensional map for an event that has spatial characteristics that approximately match spatial characteristics of the selected type of defect and determining if the event corresponds to a defect having the selected type.

    Abstract translation: 提供了用于检测相对噪声检查数据中选定缺陷的方法和系统。 一种方法包括将空间滤波器算法应用于跨越衬底上的区域获取的数据,以确定检查数据的第一部分与检查数据的第二部分相比具有较高选择类型的缺陷概率。 所选择的缺陷类型包括非点缺陷。 通过组合对应于基板上基本上相同的位置的两个或更多个原始检查数据来生成检查数据。 该方法还包括生成示出检查数据的第一部分的二维映射。 该方法还包括搜索具有近似匹配所选类型的缺陷的空间特征的空间特征的事件的二维地图,并且确定该事件是否对应于具有所选类型的缺陷。

    Systems and methods of advanced site-based nanotopography for wafer surface metrology
    8.
    发明授权
    Systems and methods of advanced site-based nanotopography for wafer surface metrology 有权
    用于晶片表面计量的先进的基于位点的纳米形貌的系统和方法

    公开(公告)号:US09177370B2

    公开(公告)日:2015-11-03

    申请号:US13779947

    申请日:2013-02-28

    CPC classification number: G06T7/0004 G06T5/20 G06T2207/20021 G06T2207/30148

    Abstract: Systems and methods for providing micro defect inspection capabilities for optical systems are disclosed. Each given wafer image is filtered, treated and normalized prior to performing surface feature detection and quantification. A partitioning scheme is utilized to partition the wafer image into a plurality of measurement sites and metric values are calculated for each of the plurality of measurement sites. Furthermore, transformation steps may also be utilized to extract additional process relevant metric values for analysis purposes.

    Abstract translation: 公开了用于为光学系统提供微缺陷检测能力的系统和方法。 在进行表面特征检测和定量之前,对每个给定的晶片图像进行过滤,处理和归一化。 利用分割方案将晶片图像分割成多个测量位置,并且为多个测量位置中的每一个计算度量值。 此外,为了分析目的,转换步骤也可以用于提取附加的过程相关度量值。

    Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool
    10.
    发明授权
    Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool 有权
    使用晶圆尺寸几何工具的晶圆高阶形状表征和晶片分类的系统,方法和度量

    公开(公告)号:US09546862B2

    公开(公告)日:2017-01-17

    申请号:US13656143

    申请日:2012-10-19

    Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

    Abstract translation: 公开了用于改善晶片高阶形状(HOS)表征和晶片分类的结果的系统和方法。 根据本公开的系统和方法基于局部形状。 将晶片图划分成多个测量点,以提高晶片形状表示的完整性。 可以针对晶片表征和/或分类目的计算各种基于站点的HOS度量值,并且还可以用作下游应用的控制输入。 此外,还提供了极坐标分割方案。 可以利用这种极性栅格划分方案将晶片表面划分成具有均匀位置区域的测量位置,同时提供良好的晶片边缘区域覆盖。

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