公开(公告)号：US08633842B2

公开(公告)日：2014-01-21

申请号：US13254397

申请日：2009-03-31

Applicant: Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

Inventor： Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

IPC: H03M3/00

CPC classification number: H03M7/3042 ,  H03M7/3024

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.

Abstract translation: 提供了使用Δ-Σ调制器直接合成RF信号的方法和装置。 通过使用诸如一位量化器的量化器量化输入信号，从输入信号合成RF信号; 确定与所述量化器相关联的量化误差; 使用误差预测滤波器生成误差预测值，其中所述误差预测滤波器包括在f1，f2的一个或多个期望频率的单位圆上的一个或多个滤波器零点。 。 。 fn和一个或多个具有在单位圆内的幅度的滤波器极，并且频率基本上等于f1，f2的一个或多个期望频率。 。 。 fn 并从输入信号中减去误差预测值。 滤波器极具有降低带外提升的幅度。

公开(公告)号：US20130028342A1

公开(公告)日：2013-01-31

申请号：US13617229

申请日：2012-09-14

Applicant: Kameran Azadet ,  Samer Hijazi ,  Sunitha Kopparthi ,  Albert Molina ,  Ramon Sanchez

Inventor： Kameran Azadet ,  Samer Hijazi ,  Sunitha Kopparthi ,  Albert Molina ,  Ramon Sanchez

IPC: H04B7/08

CPC classification number: H04L25/0202 ,  H04L1/0631 ,  H04L1/20 ,  H04L5/0023 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/021 ,  H04L25/022 ,  H04L25/023 ,  H04L25/025

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract translation: 在一个实施例中，提供接收机用于多输入系统，该多输入系统包括接收天线，其接收与从多个发射天线发射的多个信号相对应的时域信号。 接收机包括：（a）适于将时域信号变换为频域信号的变换单元; （b）信道估计单元，适于基于频域信号和频域导频信号估计与多个发射天线和接收天线之间的各个信道的多个传递函数相对应的组合传递函数 ; 以及（c）信道分离单元，其包括将所述组合传递函数分离成多个估计信道传递函数的多个频域卷积单元。

公开(公告)号：US08189704B2

公开(公告)日：2012-05-29

申请号：US12359778

申请日：2009-01-26

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H04L5/12

CPC classification number: H04L25/4923 ,  H04L25/03229 ,  H04L2025/03363

Abstract: A method and apparatus are provided for joint equalization and decoding of multilevel codes, such as the Multilevel Threshold-3 (MLT-3) code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.

Abstract translation: 提供了一种用于联合均衡和解码多级代码的方法和装置，例如在色散通道上传输的多级阈值-3（MLT-3）码。 MLT-3代码被视为由有限状态机使用在各种状态之间具有状态依赖性的网格生成的代码。 超级网格将MLT-3网格与网络格式的通道连接起来。 接收信号的联合均衡和解码可以使用超级格子进行。 公开了一种序列检测器，其使用超级格或相应的缩减状态网格来对接收到的信号进行联合均衡和解码，以解码MLT-3编码的数据位。 可以使用应用最优维特比算法或缩减复杂度序列估计方法（例如缩减状态序列估计（RSSE）算法）的最大似然序列估计来体现序列检测器。

公开(公告)号：US08121062B2

公开(公告)日：2012-02-21

申请号：US12020722

申请日：2008-01-28

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: H04B5/16

CPC classification number: H04J1/12 ,  H04J14/0298 ,  H04L5/06

Abstract: A method and apparatus are disclosed for canceling cross-talk in a frequency-division multiplexed communication system. The disclosed frequency-division multiplexed communication system employs multiple carriers having overlapping channels and provides an improved cross-talk cancellation mechanism to address the resulting interference. Bandwidth compression is achieved using n level amplitude modulation in each frequency band. An FDM receiver is also disclosed that decomposes the received broadband signal into each of its respective frequency bands and returns the signal to basehand in the analog domain. Analog requirements are relaxed by removing cross-talk from adjacent R-F channels, from image bands, and minimizing the performance degradation caused by In-phase and Quadrature-phase (I/Q) phase and gain mismatches in modulators and demodulators. The disclosed transmitter or receiver (or both) can be fabricated on a single integrated circuit.

Abstract translation: 公开了用于在频分复用通信系统中消除串扰的方法和装置。 所公开的频分复用通信系统采用具有重叠信道的多个载波，并且提供改进的串扰消除机制来解决所产生的干扰。 在每个频带中使用n级幅度调制实现带宽压缩。 还公开了一种FDM接收机，其将接收到的宽带信号分解成其各个频带的每一个，并将信号在模拟域中返回到原始信号。 通过从图像频带中消除相邻R-F信道的串扰，并将调制器和解调器中的同相和正交相（I / Q）相位和增益失配引起的性能下降最小化，从而放宽模拟需求。 公开的发射器或接收器（或两者）可以在单个集成电路上制造。

公开(公告)号：US07868798B2

公开(公告)日：2011-01-11

申请号：US12414999

申请日：2009-03-31

Applicant: Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

Inventor： Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

IPC: H03M1/20

CPC classification number: H03M7/3008 ,  H03M7/3028 ,  H03M7/3042

Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.

Abstract translation: 提供了使用抖动信号在Δ-Σ调制器中增白量化噪声的方法和装置。 使用量化器对输入信号进行量化，使用预测Δ-Σ调制器对输入信号进行量化; 在预测Δ-Σ调制器的第一位置添加抖动信号; 确定与所述量化器相关联的量化误差; 在预测Δ-Σ调制器的第二位置处去除抖动信号（例如，通过减去第二位置处的抖动信号的基本相似的版本）; 使用误差预测滤波器生成误差预测值; 并从输入信号中减去误差预测值。 抖动信号可以是白噪声信号，并且可以可选地使用伪随机数发生器来产生。

公开(公告)号：US07808329B2

公开(公告)日：2010-10-05

申请号：US12187701

申请日：2008-08-07

Applicant: Kameran Azadet ,  Fuji Yang

Inventor： Kameran Azadet ,  Fuji Yang

IPC: H03K3/03 ,  H03B27/00

CPC classification number: H03B27/00

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract translation: 提供了用于在多相时钟/定时恢复系统中改善相位线性度的方法和装置。 平均和内插技术提高了多相时钟系统的相位线性度。 根据本发明的一个方面，通过产生多个具有基本相似的频率和不同相位的时钟来产生多相输出时钟; 将多个时钟中的每一个施加到至少一个对应的放大器，例如差分对电路; 并对相应放大器的输出求和以产生多相输出时钟。 多级平均操作可以进一步提高线性度。

公开(公告)号：US20100245137A1

公开(公告)日：2010-09-30

申请号：US12415003

申请日：2009-03-31

Applicant: Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

Inventor： Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

IPC: H03M3/00

CPC classification number: H03M7/3042

Abstract: Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values.

Abstract translation: 提供了用于预测Δ-Σ调制器中的先行块处理的方法和装置。 基于来自一个或多个先前块的误差预测值的线性组合，一个或多个先前块的输入值，量化的输入信号，通过使用预测Δ-Σ调制器来量化当前块的输入值的误差预测值 一个或多个先前块的值和当前的输入值块; 计算当前块中的至少一个输入值的推测误差预测值，其中针对多个可能的量化器输出值计算推测误差预测值; 基于来自当前块的量化值选择推测性误差预测值之一; 以及从相应的当前输入值块中减去当前块的误差预测值。

公开(公告)号：US20100245136A1

公开(公告)日：2010-09-30

申请号：US12414999

申请日：2009-03-31

Applicant: Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

Inventor： Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

IPC: H03M3/00 ,  H03M1/06

CPC classification number: H03M7/3008 ,  H03M7/3028 ,  H03M7/3042

Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.

Abstract translation: 提供了使用抖动信号在Δ-Σ调制器中增白量化噪声的方法和装置。 使用量化器对输入信号进行量化，使用预测Δ-Σ调制器对输入信号进行量化; 在预测Δ-Σ调制器的第一位置添加抖动信号; 确定与所述量化器相关联的量化误差; 在预测Δ-Σ调制器的第二位置处去除抖动信号（例如，通过减去第二位置处的抖动信号的基本相似的版本）; 使用误差预测滤波器生成误差预测值; 并从输入信号中减去误差预测值。 抖动信号可以是白噪声信号，并且可以可选地使用伪随机数发生器来产生。

公开(公告)号：US20100198893A1

公开(公告)日：2010-08-05

申请号：US12362874

申请日：2009-01-30

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F7/00 ,  G06F7/52

CPC classification number: G06F7/556 ,  G06F1/035 ,  G06F2101/10

Abstract: A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.

Abstract translation: 提供了一种数字信号处理器，其具有使用减少的查找表的具有xK功能的指令集。 所公开的数字信号处理器通过在硬件中计算Log（x）来评估输入值x的xK函数; 将Log（x）值乘以K; 以及通过在硬件中对乘法步骤的结果应用指数函数来确定xK函数。 Log（x）和指数函数的计算中的一个或多个使用至少一个查找表，其具有比输入值x中的位数少的位数较少的条目。

公开(公告)号：US20100138464A1

公开(公告)日：2010-06-03

申请号：US12324931

申请日：2008-11-28

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F17/17

CPC classification number: G06F17/10 ,  G06F1/035 ,  G06F9/3001 ,  G06F9/383

Abstract: A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size and exponentially varying step-sizes. A digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for the non-linear function that are near the value, x, wherein the at least one look-up table stores a subset of values for the non-linear function using exponentially-varying step sizes; and interpolating the at least two obtained values lo to obtain a result, y. A position of a leading zero in the value, x, can be used as an index into the at least one look-up table. The interpolation can comprise, for example, a linear interpolation or a polynomial interpolation. A modulo arithmetic operation can optionally be employed for a periodic non-linear function.

Abstract translation: 公开了一种数字信号处理器和方法，其具有使用减小尺寸和指数级变化的步长的查找表的具有一个或多个非线性函数的指令集。 数字信号处理器通过从近似于值x的非线性函数的至少一个查找表中获得至少两个值来评估值x的非线性函数，其中至少一个外观 -up表使用指数变化的步长存储用于非线性函数的值的子集; 并且内插所述至少两个获得的值lo以获得结果y。 值x中的前导零的位置可以用作至少一个查找表中的索引。 内插可以包括例如线性内插或多项式插值。 对于周期性非线性函数可以可选地使用模运算。