公开(公告)号：US20230198547A1

公开(公告)日：2023-06-22

申请号：US18085066

申请日：2022-12-20

申请人： University College Dublin

发明人： Valerio Mazzaro ,  Michael Peter Kennedy

IPC分类号： H03M7/32 ,  H03M7/36

CPC分类号： H03M7/3008 ,  H03M7/3026

摘要： An apparatus for mitigating nonlinearity-induced spurs and noise in a fractional-N frequency synthesizer
A digital delta-sigma modulator (DDSM) is disclosed with an input signal x[n], an output signal y[n], a quantization error signal e[n] and a dither signal d[n], having an equation described in the z-domain by


Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z)

wherein Y(z), X(z), D(z) andE(z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF (z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form:





NTF
⁡
(
z
)

=



Az

-
Q


(

1
-

z

-
1



)

⁢

(

1
+


∑

i
=
1

K



c
i

⁢

z

-
i





)






where A , Q and K are constants, coefficients ci are real valued and cK≠0 and wherein at least one of the zeroes zj of




(

1
+


∑

i
=
1

K



c
i

⁢

z

-
i





)




satisfies zj≠+1 for j=1, 2, . . . , K

公开(公告)号：US07876247B1

公开(公告)日：2011-01-25

申请号：US12325223

申请日：2008-11-30

申请人： Shawn David Hunt ,  Carlos Fabian Benitez-Quiroz

发明人： Shawn David Hunt ,  Carlos Fabian Benitez-Quiroz

IPC分类号： H03M1/20

CPC分类号： H03M7/3008 ,  H03M7/3024

摘要： A new technique on the dithering of one-dimensional signals is presented. The novel technique determines whether dither is needed when reducing the bit depth and evaluates whether the total error of the un-dithered quantization is white noise. If this is the case, then no undesired harmonics are added in the quantization or re-quantization process. The novel technique presents a state of the art signal-dependent dither having a lower quantization noise.

摘要翻译： 提出了一种关于一维信号抖动的新技术。 该新颖的技术确定了在减少比特深度时需要抖动，并且评估未抖动量化的总误差是否为白噪声。 如果是这种情况，则在量化或重新量化过程中不会添加不期望的谐波。 该新技术呈现出具有较低量化噪声的最先进的信号相关抖动。

公开(公告)号：US20080175333A1

公开(公告)日：2008-07-24

申请号：US12039993

申请日：2008-02-29

申请人： Henrik Jensen ,  Alireza Zolfaghari

发明人： Henrik Jensen ,  Alireza Zolfaghari

IPC分类号： H04L27/02 ,  H03M3/00

CPC分类号： H03M7/3008 ,  H03M1/0673 ,  H03M3/502 ,  H03M7/3026 ,  H03M7/3042 ,  H04L27/361

摘要： Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

摘要翻译： 提出了用于功率放大器驱动器幅度调制的数模转换方法和系统的方面。 系统的各个方面可以包括能够在单个集成电路装置内对数字基带信号中的多个采样中的每一个进行过采样的电路。 该电路可以使得在每个过采样的多个采样中减少多个位，即粗略量化，以便导致作为粗量化的结果而发生的量化噪声的位移。 可以基于过采样信号产生后续信号。 该电路可以使得后续信号可以利用单个集成电路器件中的滤波器电路进行低通滤波，从而衰减位移到过采样信号的较高频率范围内的量化噪声。

公开(公告)号：US20040119619A1

公开(公告)日：2004-06-24

申请号：US10731667

申请日：2003-12-09

发明人： Russell H. Lambert

IPC分类号： H03M001/02

CPC分类号： H04W88/06 ,  H03M3/332 ,  H03M3/334 ,  H03M3/336 ,  H03M3/43 ,  H03M3/456 ,  H03M3/50 ,  H03M7/3008 ,  H03M7/3028 ,  H03M7/304 ,  H04W84/12

摘要： An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock reduction circuit. The modulator receives the analog signal and a feedback signal and, based there upon, produces a modulated signal at a modulator clock rate. The decimation filter couples to the modulator, receives the modulated signal, and decimates and filters the modulated signal to produce the digital data. The time dither clock reduction circuit receives the modulated signal and provides the feedback signal to the modulator. The time dither clock reduction circuit applies both clock reduction and time dithering to the modulated signal to produce the feedback signal. At each modulator clock cycle, the time dithering clock reduction circuit considers modulated signals for a dithering factor, N, previous modulator clock cycles and a modulated signal for a current modulator clock cycle. If at least one constraint is satisfied for the N previous modulator clock cycles, the time dithering clock reduction circuit is allowed to transition the feedback signal with the modulated signal. If not, the time dithering clock reduction circuit holds the prior value of the feedback signal. After a transition, a new dithering factor may be determined. The ADC may be contained in a wireless local area network (WLAN) transceiving integrated circuit that services voice communications in a WLAN with at least one other WLAN device.

摘要翻译： 模数转换器（ADC）将模拟信号转换为数字数据。 ADC包括调制器，抽取滤波器和时间抖动时钟降低电路。 调制器接收模拟信号和反馈信号，并且基于此，以调制器时钟速率产生调制信号。 抽取滤波器耦合到调制器，接收调制信号，并抽取和滤波调制信号以产生数字数据。 时间抖动时钟降低电路接收调制信号并向调制器提供反馈信号。 时间抖动时钟降低电路将时钟减少和时间抖动应用于调制信号以产生反馈信号。 在每个调制器时钟周期，时间抖动时钟降低电路考虑用于抖动因子N的调制信号，先前的调制器时钟周期和用于当前调制器时钟周期的调制信号。 如果对于N个先前的调制器时钟周期满足至少一个约束，则允许时间抖动时钟降低电路用调制信号转换反馈信号。 如果不是，则时间抖动时钟降低电路保持反馈信号的先前值。 转换后，可以确定新的抖动因子。 ADC可以包含在用至少一个其它WLAN设备来服务WLAN中的语音通信的无线局域网（WLAN）收发集成电路中。

公开(公告)号：US5252973A

公开(公告)日：1993-10-12

申请号：US902643

申请日：1992-06-23

申请人： Toshishiko Masuda

发明人： Toshishiko Masuda

IPC分类号： H03M1/10 ,  H03M3/02 ,  H03M7/34 ,  H03M1/20

CPC分类号： H03M7/3006 ,  H03M7/3008 ,  H03M7/3026 ,  H03M7/3042

摘要： An apparatus for digital-to-analogue conversion. A dither generator creates a noise signal which is added to a digital input signal to produce an added output. Noise shaping is performed on the added output at a noise shaping circuit. The noise shaping circuit includes a quantizer with certain threshold levels for quantizing the added signal. A digital-to-analogue (D/A) converter converts the output of the noise shaping circuit to an analog signal. A control circuit widens the threshold levels as a level of the digital input signal becomes zero, and attenuates an input signal to the digital-to-analogue converter by about 1/K times when the threshold levels are increased by K times.

摘要翻译： 一种用于数模转换的装置。 抖动发生器产生噪声信号，该噪声信号被添加到数字输入信号以产生附加的输出。 在噪声整形电路的附加输出上执行噪声整形。 噪声整形电路包括具有用于量化附加信号的某些阈值电平的量化器。 数模（D / A）转换器将噪声整形电路的输出转换为模拟信号。 当阈值电平增加K倍时，控制电路随着数字输入信号的电平变为零而加宽阈值电平，并将数模转换器的输入信号衰减大约1 / K倍。

公开(公告)号：US07548180B2

公开(公告)日：2009-06-16

申请号：US12039993

申请日：2008-02-29

申请人： Henrik Jensen ,  Alireza Zolfaghari

发明人： Henrik Jensen ,  Alireza Zolfaghari

IPC分类号： H03M3/00

CPC分类号： H03M7/3008 ,  H03M1/0673 ,  H03M3/502 ,  H03M7/3026 ,  H03M7/3042 ,  H04L27/361

摘要： Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

摘要翻译： 提出了用于功率放大器驱动器幅度调制的数模转换方法和系统的方面。 系统的各个方面可以包括能够在单个集成电路装置内对数字基带信号中的多个采样中的每一个进行过采样的电路。 该电路可以使得在每个过采样的多个采样中减少多个位，即粗略量化，以便导致作为粗量化的结果而发生的量化噪声的位移。 可以基于过采样信号产生后续信号。 电路可以使得随后的信号可以利用单个集成电路器件中的滤波器电路进行低通滤波，从而衰减位移到过采样信号的较高频率范围内的量化噪声。

公开(公告)号：US07471223B2

公开(公告)日：2008-12-30

申请号：US11506515

申请日：2006-08-18

申请人： Yong-Hee Lee

发明人： Yong-Hee Lee

IPC分类号： H03M1/20

CPC分类号： H03M3/332 ,  H03M3/424 ,  H03M3/43 ,  H03M3/458 ,  H03M3/50 ,  H03M7/3008 ,  H03M7/3026 ,  H03M7/3028

摘要： A delta-sigma modulator circuit includes an n-level quantizer circuit that is configured to generate a quantized output signal responsive to an input signal. The n-level quantizer circuit includes n adder circuits that are configured to add a dither signal to n quantization levels to generate n dithered quantization levels, respectively and n comparator circuits that are configured to compare the input signal with the n dithered quantization levels to generate the quantized output signal.

摘要翻译： Δ-Σ调制器电路包括被配置为响应于输入信号产生量化输出信号的n电平量化器电路。 n电平量化器电路包括n个加法器电路，其被配置为将抖动信号分别加到n个量化电平以分别产生n个抖动量化电平，以及n个比较器电路，其被配置为将输入信号与n个抖动量化电平进行比较以产生 量化输出信号。

公开(公告)号：US07362251B2

公开(公告)日：2008-04-22

申请号：US11436348

申请日：2006-05-18

申请人： Henrik Jensen ,  Alireza Zolfaghari

发明人： Henrik Jensen ,  Alireza Zolfaghari

IPC分类号： H03M3/00

CPC分类号： H03M7/3008 ,  H03M1/0673 ,  H03M3/502 ,  H03M7/3026 ,  H03M7/3042 ,  H04L27/361

摘要： Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

摘要翻译： 提出了用于功率放大器驱动器幅度调制的数模转换方法和系统的方面。 系统的各个方面可以包括能够在单个集成电路装置内对数字基带信号中的多个采样中的每一个进行过采样的电路。 该电路可以使得在每个过采样的多个采样中减少多个位，即粗略量化，以便导致作为粗量化的结果而发生的量化噪声的位移。 可以基于过采样信号产生后续信号。 该电路可以使得后续信号可以利用单个集成电路器件中的滤波器电路进行低通滤波，从而衰减位移到过采样信号的较高频率范围内的量化噪声。

公开(公告)号：US07031401B2

公开(公告)日：2006-04-18

申请号：US10230738

申请日：2002-08-29

申请人： Russell H. Lambert

发明人： Russell H. Lambert

IPC分类号： H04L27/04 ,  H03M1/00

CPC分类号： H04W88/06 ,  H03M3/332 ,  H03M3/334 ,  H03M3/336 ,  H03M3/43 ,  H03M3/456 ,  H03M3/50 ,  H03M7/3008 ,  H03M7/3028 ,  H03M7/304 ,  H04W84/12

摘要： A Digital-to-Analog-Converter (DAC) includes an interpolation filter, a modulator, and a time dither clock reduction circuit. The interpolation filter receives the digital data and interpolates and filters the digital data to produce an interpolated and filtered digital signal. The modulator receives the interpolated and filtered digital signal and a feedback signal. The modulator modulates the interpolated and filtered digital signal based upon the feedback signal to produce a modulated signal at a modulator clock rate. The time dither clock reduction circuit receives the modulated signal and applies both clock reduction and time dithering to the modulated signal to produce a time dithered/clock reduced modulated signal. The time dithered/clock reduced modulated signal serves as the analog signal and also serves as the feedback signal. The DAC may be contained in a wireless local area network (WLAN) transceiving integrated circuit that services voice communications in a WLAN with at least one other WLAN device.

公开(公告)号：US20040239417A1

公开(公告)日：2004-12-02

申请号：US10768365

申请日：2004-01-29

发明人： Venkateswar R. Kowkutla ,  Shifeng Zhao ,  Luis E. Ossa ,  Kenneth M. Bell ,  Anker Josefsen ,  Lars Risbo

IPC分类号： H03F003/38

CPC分类号： H03M7/3008 ,  H03F3/2171 ,  H03F3/2173 ,  H03M7/3042

摘要： A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

摘要翻译： 数字放大器包括噪声整形器和布置成对成形器引入噪声的抖动发生器。 生成器使用从整形器的状态变量导出的种子值。