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公开(公告)号：US20090179697A1
公开(公告)日：2009-07-16
申请号：US12013070
申请日：2008-01-11
申请人： Thomas J. Zuiss , Kevin B. Traylor
发明人： Thomas J. Zuiss , Kevin B. Traylor
IPC分类号： H03F3/38
CPC分类号： H03F3/68 , H03F3/185 , H03F3/2171
摘要： An amplifier comprises first, second, and third modulators. The first modulator includes an input for receiving a first input signal, and an output for providing a first modulated output signal corresponding to the first input signal. The second modulator includes an input for receiving a second input signal, and an output for providing a second modulated output signal corresponding to the second input signal. The third modulator has an input for receiving a third input signal, and an output for providing a third modulated output signal corresponding to the third input signal and for providing a virtual ground. A first amplifier circuit is coupled to the outputs of the first and third modulators for driving a first load. A second amplifier circuit is coupled to the outputs of the second and third modulators for driving a second load.
摘要翻译： 放大器包括第一，第二和第三调制器。 第一调制器包括用于接收第一输入信号的输入端和用于提供对应于第一输入信号的第一调制输出信号的输出端。 第二调制器包括用于接收第二输入信号的输入端和用于提供对应于第二输入信号的第二调制输出信号的输出端。 第三调制器具有用于接收第三输入信号的输入端和用于提供对应于第三输入信号的第三调制输出信号并用于提供虚拟接地的输出端。 第一放大器电路耦合到第一和第三调制器的输出端，用于驱动第一负载。 第二放大器电路耦合到第二和第三调制器的输出端，用于驱动第二负载。
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公开(公告)号：US20070300043A1
公开(公告)日：2007-12-27
申请号：US11426630
申请日：2006-06-27
申请人： William C. Moyer , Kevin B. Traylor
发明人： William C. Moyer , Kevin B. Traylor
IPC分类号： G06F15/00
CPC分类号： G06F9/3001 , G06F9/3824 , G06F9/3826 , G06F9/3877
摘要： A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
摘要翻译： 协处理器（14）可用于执行可以从主要或通用处理器（12）卸载的一个或多个专门操作。 允许处理器（12）和协处理器（14）之间的高效通信和接口是重要的。 在一个实施例中，协处理器（14）产生并向处理器（12）中的指令管道（20）提供指令（200,220）。 由于协处理器（14）产生的指令是处理器（12）的标准指令集的一部分，所以高速缓存（70）的一致性容易维护。 而且，协处理器（14）中的电路（102）可以对数据执行操作，而协处理器（14）中的电路（106）同时产生处理器指令（200,220）。
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23.发明授权Speech-operated noise attenuation device (SONAD) control system method and apparatus 失效语音操作噪声衰减装置（SONAD）控制系统的方法和装置
公开(公告)号：US6115589A
公开(公告)日：2000-09-05
申请号：US841242
申请日：1997-04-29
申请人： Enrique Ferrer , Charles R. Ruelke , Andrew J. Webster , Kenneth A. Hansen , Rajesh H. Zele , Kevin B. Traylor
发明人： Enrique Ferrer , Charles R. Ruelke , Andrew J. Webster , Kenneth A. Hansen , Rajesh H. Zele , Kevin B. Traylor
CPC分类号： H03G3/341 , H03G3/001 , H04B1/1661
摘要： A SONAD (110) control system (100) detects a received signal strength (RSSI) for a radio frequency (RF) signal (102), selects a threshold transfer function (400-404) in response thereto, generates a threshold control signal in response to the transfer function, and utilizes the threshold control signal to select the SONAD threshold value. During operation, the control system (100) decreases the attenuation of background noise levels for weak RF signals.
摘要翻译： SONAD（110）控制系统（100）检测射频（RF）信号（102）的接收信号强度（RSSI），响应于此选择阈值传递函数（400-404），产生阈值控制信号 响应于传递函数，并利用阈值控制信号选择SONAD阈值。 在操作期间，控制系统（100）降低弱RF信号的背景噪声电平的衰减。
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公开(公告)号：US5418489A
公开(公告)日：1995-05-23
申请号：US134197
申请日：1993-10-08
申请人： Kevin B. Traylor
发明人： Kevin B. Traylor
CPC分类号： H03D3/007 , H03D7/166 , H03D2200/0039 , H03D2200/0072 , H03D2200/0082 , H03D3/22
摘要： An apparatus and method is provided of recovering a frequency modulated signal having a first component of the frequency modulated signal at a zero-RF spectral location and a second component of the frequency modulated signal at a zero-RF spectral location in quadrature relationship to the first component. The method includes the steps of: upconverting and summing the first and second components to produce a reference signal (100), time delaying the first and second components, upconverting and summing the delayed, upconverted first and second components to produce a delayed reference signal (101) in quadrature relationship to the reference signal; limiting the reference and delayed signal (102); and exclusive or-ing (103) the limited reference and limited delayed signal.
摘要翻译： 提供了一种装置和方法，用于在零RF频谱位置处恢复具有频率调制信号的第一分量的频率调制信号，并将频率调制信号的第二分量与正交关系的零RF频谱位置恢复到第一 零件。 该方法包括以下步骤：对第一和第二分量进行上变频和求和以产生参考信号（100），对第一和第二分量进行时间延迟，对延迟的上变频的第一和第二分量进行上变频和加法，以产生延迟的参考信号（ 101）与参考信号成正交关系; 限制参考和延迟信号（102）; 并且限制（103）有限的参考和有限的延迟信号。
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公开(公告)号：US09106499B2
公开(公告)日：2015-08-11
申请号：US13924996
申请日：2013-06-24
CPC分类号： H04L27/2662 , H04B3/54 , H04L27/2656 , H04L27/2672 , H04L27/2675 , H04L27/2688
摘要： Methods and systems are disclosed for frequency-domain frame synchronization for multi-carrier communication systems. Received signals are sampled and converted into frequency domain components associated with subcarriers within the multi-carrier communication signals. A sliding-window correlation (e.g., two-dimensional sliding window) is applied to the received symbols represented in the frequency domain to detect frame boundaries for multi-carrier signals. The sliding-window frame synchronization can be applied by itself or can be applied in combination with one or more additional frame synchronization stages. The disclosed embodiments are particularly useful for frame synchronization of multi-carrier signals in PLC (power line communication) systems.
摘要翻译： 公开了用于多载波通信系统的频域帧同步的方法和系统。 接收的信号被采样并转换成与多载波通信信号内的子载波相关联的频域分量。 将滑窗相关（例如，二维滑动窗口）应用于在频域中表示的接收符号，以检测多载波信号的帧边界。 滑动窗口帧同步可以自己应用或者可以与一个或多个附加帧同步阶段组合应用。 所公开的实施例对于PLC（电力线通信）系统中的多载波信号的帧同步特别有用。
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公开(公告)号：US20140376667A1
公开(公告)日：2014-12-25
申请号：US13924940
申请日：2013-06-24
IPC分类号： H04L27/26
CPC分类号： H04L27/2657 , H04L25/03159 , H04L27/2647
摘要： Methods and systems are disclosed for frequency-domain carrier blanking in multi-carrier communication systems. When excessive energy is detected in one or more subcarriers within a received symbol for multi-carrier communications, those subcarriers are blanked for subsequent demodulation in order to avoid corruption of the demodulated data. A conversion from time-domain digital samples to frequency-domain values using an FFT (Fast Fourier Transform) and a threshold detector are utilized to detect corrupted subcarriers. Further, this frequency-domain carrier blanking can be implemented dynamically on a symbol-by-symbol basis to further improve demodulation performance by reducing decoding errors. The disclosed embodiments are particularly useful for improving demodulation performance in power line communication (PLC) systems.
摘要翻译： 公开了用于多载波通信系统中的频域载波消隐的方法和系统。 当在用于多载波通信的接收符号内的一个或多个子载波中检测到过多的能量时，为了后续解调，将这些子载波消隐以避免解调数据的损坏。 利用FFT（快速傅里叶变换）和阈值检测器将时域数字样本转换为频域值，以检测损坏的子载波。 此外，该频域载波消隐可以逐个符号地动态地实现，以通过减少解码错误来进一步提高解调性能。 所公开的实施例对于改善电力线通信（PLC）系统中的解调性能特别有用。
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公开(公告)号：US08181098B2
公开(公告)日：2012-05-15
申请号：US12157512
申请日：2008-06-11
IPC分类号： G06F11/00
CPC分类号： H03M13/4115 , H03M13/09 , H03M13/27 , H03M13/41 , H03M13/6362 , H04L1/0054
摘要： Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.
摘要翻译： 维特比解码器中的方法和对应系统包括响应于执行第一维特比算法计算维特比网格中的最大似然（ML）路径。 此后，在第二维特比算法中在ML路径上选择一个或多个合并点，其中合并点各自具有路径度量差异，其是合并点处的ML路径度量与不存在路径度量 在合并点。 基于与ML路径上的节点相关联的相对路径度量差选择合并点。 接下来，维特比网格中的替代路径是基于ML路径计算的，其中替代路径在相应的合并点处被替换。 经过解码的比特序列响应于通过错误检查被输出，其中通过解码的比特序列与一个或多个替代路径中的一个相关联。
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公开(公告)号：US08099657B2
公开(公告)日：2012-01-17
申请号：US12218183
申请日：2008-07-11
IPC分类号： H03M13/03
CPC分类号： H04L1/0054 , H03M13/3738 , H03M13/3746 , H03M13/41 , H04L1/0052
摘要： Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
摘要翻译： 维特比解码器中的方法和对应系统包括选择输入块中的输入符号，其中输入块具有多个输入符号，其中每个输入符号具有布尔值，质量值和相关级，并且其中 基于所选符号的质量值相对于输入块中的其他输入符号的质量值来选择所选择的符号。 此后，补充所选符号的布尔值以产生补码。 替代了所选符号以产生替代输入块。 使用替代输入块执行维特比算法来产生替代解码比特序列，然后使用错误检查来检查错误。 响应于通过错误检查的替代解码比特序列输出替代解码比特序列。
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29.发明授权Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges 有权当程序计数器值落在预定范围内时，协处理器将加载和存储具有位移的指令传送到主处理器用于缓存一致执行公开(公告)号：US07925862B2
公开(公告)日：2011-04-12
申请号：US11426630
申请日：2006-06-27
申请人： William C. Moyer , Kevin B. Traylor
发明人： William C. Moyer , Kevin B. Traylor
IPC分类号： G06F9/312
CPC分类号： G06F9/3001 , G06F9/3824 , G06F9/3826 , G06F9/3877
摘要： A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
摘要翻译： 协处理器（14）可用于执行可以从主要或通用处理器（12）卸载的一个或多个专门操作。 允许处理器（12）和协处理器（14）之间的高效通信和接口是重要的。 在一个实施例中，协处理器（14）产生并向处理器（12）中的指令管道（20）提供指令（200,220）。 由于协处理器（14）产生的指令是处理器（12）的标准指令集的一部分，所以高速缓存（70）的一致性容易维护。 而且，协处理器（14）中的电路（102）可以对数据执行操作，而协处理器（14）中的电路（106）同时产生处理器指令（200,220）。
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30.发明申请TECHNIQUES FOR PERFORMING DISCRETE FOURIER TRANSFORMS ON RADIX-2 PLATFORMS 有权在RADIX-2平台上执行离散傅立叶变换的技术公开(公告)号：US20090313314A1
公开(公告)日：2009-12-17
申请号：US12140890
申请日：2008-06-17
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.
摘要翻译： 用于执行离散傅里叶变换（DFT）的技术包括在单端口存储器中存储多个信号点。 将多个信号点中的连续的多个信号点中的第一组（从单端口存储器的第一行）提取到与包括多个运算单元（AU）的处理器相关联的第一输入寄存器，每个运算单元被配置为执行乘法累积 （MAC）操作。 然后将多个信号点中的第二组连续的信号点从单端口存储器的第二行提取到与处理器相关联的第二输入寄存器。 然后，在初始蝴蝶阶段期间，将多个信号点的所选择的对加载（每对中的每个第一和第二输入寄存器中的一个）分配到多个运算单元中。 然后对所选择的多个信号点对（使用多个AU）执行基2蝶形运算，以提供相应的输出元件。
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