公开(公告)号：US20050204088A1

公开(公告)日：2005-09-15

申请号：US11051449

申请日：2005-02-04

申请人： Kuan-Jui Ho ,  Stephen Chen ,  Ruei-Ling Lin ,  Chien-Ping Chung

发明人： Kuan-Jui Ho ,  Stephen Chen ,  Ruei-Ling Lin ,  Chien-Ping Chung

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： Data acquisition methods and systems in support of non-snoop transactions. In the data acquisition method, the cache memory is partially written back and invalidate, such that a portion of the data in the cache memory is written back to the DMA buffer. The endpoint device is directed to use a non-snoop transaction to read the data stored in the DMA buffer. The data stored in the DMA buffer is acquired directly without snooping the processor when receiving a non-snoop read transaction.

摘要翻译： 数据采集​​方法和系统支持非侦听事务。 在数据采集方法中，高速缓冲存储器部分地被写回并使其无效，使得高速缓冲存储器中的一部分数据被写回到DMA缓冲器。 端点设备被指示使用非窥探事务来读取存储在DMA缓冲器中的数据。 存储在DMA缓冲器中的数据直接获取，而不会在接收到非窥探读取事务时窥探处理器。

公开(公告)号：US08131907B2

公开(公告)日：2012-03-06

申请号：US12545284

申请日：2009-08-21

申请人： Kuan-Jui Ho

发明人： Kuan-Jui Ho

IPC分类号： G06F13/36

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

摘要： A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

摘要翻译： 提供了一种多处理器系统及其动态省电方法。 多处理器系统包括多个处理器和芯片组。 每个处理器具有多个标准总线请求引脚和特定总线请求引脚，并且每个处理器的标准总线请求引脚分别交替地连接到其他处理器的标准总线请求引脚。 芯片组耦合到处理器的特定总线请求引脚，用于检测特定总线请求引脚上的控制请求信号。 当芯片组检测到控制请求信号时，芯片组打开与处理器连接的输入缓冲器，使得处理器可以通过输入缓冲器访问数据。 当芯片组未检测到控制请求信号时，芯片组关闭输入缓冲器。

公开(公告)号：US07634669B2

公开(公告)日：2009-12-15

申请号：US11316708

申请日：2005-12-27

申请人： Kuan-Jui Ho

发明人： Kuan-Jui Ho

IPC分类号： G06F1/32

CPC分类号： G06F1/3203

摘要： A method of power management of a CPU connects to a plurality of host bridges. The method is applied to a CPU connecting to the host bridges. When the host bridges are detected as no bus master signal being received, a command is transmitted to force the host bridges not to transmit the bus master signal to the CPU when they receive the bus master signal. After the CPU enters the C3 state, if the host bridges are detected that any one of the host bridges receives the bus master signal, the CPU is forced to quit the C3 state, and the host bridges are forced to transmit the bus master signal to the CPU.

摘要翻译： CPU的电源管理方法连接到多个主机桥。 该方法应用于连接到主机桥的CPU。 当主机桥被检测为没有接收到总线主机信号时，发送命令以强制主机桥接器不接收总线主机信号时将总线主机信号发送到CPU。 在CPU进入C3状态之后，如果检测到主机桥接任何一个主机桥接收总线主机信号，则CPU被迫退出C3状态，并且主机桥被强制传送总线主机信号到 CPU。

公开(公告)号：US07447827B2

公开(公告)日：2008-11-04

申请号：US11414219

申请日：2006-05-01

申请人： Jen-Chieh Chen ,  Kuan-Jui Ho

发明人： Jen-Chieh Chen ,  Kuan-Jui Ho

IPC分类号： G06F13/00

CPC分类号： G06F13/404

摘要： A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP bus. The second bridge is electrically connected between the first AGP bus and the PCI bus. The controller is electrically connected to the first AGP bus, the first bridge, and the second bridge. As a configuration cycle corresponding to the first bridge being transmitted through the first AGP bus to the controller, the controller responds a preset message implying that the first bridge does not exist.

摘要翻译： 提供电连接到第一AGP总线，第二AGP总线和PCI总线的桥接器件。 桥接器件具有第一桥，第二桥和控制器。 第一桥电连接在第一AGP总线和第二AGP总线之间。 第二桥电连接在第一AGP总线和PCI总线之间。 控制器电连接到第一AGP总线，第一桥和第二桥。 作为与通过第一AGP总线传送到控制器的第一桥相对应的配置周期，控制器响应预设消息，暗示第一桥不存在。

公开(公告)号：US07412582B2

公开(公告)日：2008-08-12

申请号：US11127113

申请日：2005-05-12

申请人： Kuan-Jui Ho ,  Hsiu Ming Chu

发明人： Kuan-Jui Ho ,  Hsiu Ming Chu

IPC分类号： G06F12/04

CPC分类号： G06F13/28 ,  G06F12/0879

摘要： A device for burst reading/writing memory data includes a memory module and a north bridge chipset. The device is used for executing a power on self test (POST). The memory module has a plurality of memory cells and the north bridge chipset includes a programmable register module and a memory module controller, wherein the programmable register module stores at least one set of default information. The memory module controller performing burst read/write on the memory cells according to the default information stored in the programmable register module.

摘要翻译： 用于突发读/写存储器数据的装置包括存储器模块和北桥芯片组。 该设备用于执行电源自检（POST）。 存储器模块具有多个存储器单元，并且北桥芯片组包括可编程寄存器模块和存储器模块控制器，其中可编程寄存器模块存储至少一组默认信息。 存储器模块控制器根据存储在可编程寄存器模块中的默认信息在存储器单元上执行脉冲串读/写。

公开(公告)号：US20080034380A1

公开(公告)日：2008-02-07

申请号：US11832253

申请日：2007-08-01

申请人： Kuan-Jui Ho

发明人： Kuan-Jui Ho

IPC分类号： G06F13/12

CPC分类号： G06F11/1076 ,  G06F2211/1054

摘要： In a computer system including a central processing unit, a system memory, a south bridge module, a north bridge module and multiple hard disk drives, a RAID control function is exhibited. The method includes steps of: issuing a command addressing to the south bridge module by the central processing unit; and performing a fault-tolerant computing operation in the north bridge module while exempting from transmitting the command to the south bridge module when the command contains a specified address data.

摘要翻译： 在包括中央处理单元，系统存储器，南桥模块，北桥模块和多个硬盘驱动器的计算机系统中，显示了RAID控制功能。 该方法包括以下步骤：由中央处理单元向南桥模块发出寻址命令; 并且在所述命令包含指定的地址数据时，在所述北桥模块中执行容错计算操作，同时不向所述南桥模块发送所述命令。

公开(公告)号：US07325085B2

公开(公告)日：2008-01-29

申请号：US11263970

申请日：2005-11-02

申请人： Hsiu Ming Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

发明人： Hsiu Ming Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

IPC分类号： G06F13/36

CPC分类号： G06F9/4411

摘要： A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.

摘要翻译： 主板包括南桥芯片组，北桥芯片组和中央处理器单元（CPU）。 南桥芯片组至少产生控制设置数据。 北桥芯片组具有用于控制北桥芯片组以产生复位信号的复位寄存器和用于存储由南桥芯片组产生的控制设置数据的控制集合寄存器。 CPU具有多个配置参数。 CPU的配置参数根据复位信号复位，控制设置数据由北桥芯片组写入CPU，以设置CPU的一个配置参数。

公开(公告)号：US07216245B2

公开(公告)日：2007-05-08

申请号：US10803323

申请日：2004-03-18

申请人： Ming-Wei Hsu ,  Kuan-Jui Ho

发明人： Ming-Wei Hsu ,  Kuan-Jui Ho

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/325 ,  Y02D10/128

摘要： A computer system with power management and the method thereof. First, the CPU outputs a power management signal to the south bridge. The south bridge responds with a stop clock signal, and then the CPU responds with a stop grant message. The north bridge receives and analyzes the stop grant message to identify a power supply mode. If the power supply mode is to suspend the main power supplied from the power supply, the north bridge outputs a state transition signal to the peripheral, which then responds with an acknowledge signal. The north bridge passes the stop grant message to the south bridge after receiving the acknowledge signal. The south bridge receives the stop grant message and outputs a power control signal accordingly. The power supply receives the power control signal for suspending the corresponding power accordingly.

摘要翻译： 一种具有电源管理的计算机系统及其方法。 首先，CPU向南桥输出电源管理信号。 南桥响应一个停止时钟信号，然后CPU响应一个停止授权消息。 北桥接收并分析停止授权信息，以识别电源模式。 如果电源模式暂停从电源提供的主电源，则北桥向外设输出状态转换信号，然后响应确认信号。 北桥在收到确认信号后，通过南桥的停车许可信息。 南桥接收停止授权信息，并相应地输出功率控制信号。 电源接收功率控制信号，以相应地中断相应的功率。

公开(公告)号：US20070005952A1

公开(公告)日：2007-01-04

申请号：US11476712

申请日：2006-06-29

申请人： Kuan-Jui Ho

发明人： Kuan-Jui Ho

IPC分类号： G06F9/00

CPC分类号： G06F9/4401

摘要： A boot-up method for a computer system comprises the steps of after turning on the power on the system, a Central Process Unit (CPU) accessing the Basic Input/Output System (BIOS) within the Read Only Memory (ROM) to execute the boot-up self-testing procedure; enabling a cache memory for assisting to quickly execute the initial procedure for the chipset and the system memory; after finishing the initial procedure of the system memory, disabling the cache memory for returning to the general status of the system; executing the initial procedure of the cache memory and other peripheral devices for finishing the boot-up procedure, such that can achieve the purpose of fast boot-up for the system and ensuring the system stability.

摘要翻译： 一种用于计算机系统的启动方法包括以下步骤：在接通系统电源之后，中央处理单元（CPU）访问只读存储器（ROM）内的基本输入/输出系统（BIOS）以执行 启动自检程序; 启用高速缓冲存储器以帮助快速执行芯片组和系统存储器的初始过程; 在完成系统内存的初始过程之后，禁用高速缓冲存储器返回到系统的一般状态; 执行高速缓冲存储器和其他外围设备的初始过程，以完成启动过程，从而可以实现系统快速启动的目的，并确保系统的稳定性。

公开(公告)号：US20070005949A1

公开(公告)日：2007-01-04

申请号：US11162602

申请日：2005-09-16

申请人： Kuan-Jui Ho ,  Ming-Wei Hsu

发明人： Kuan-Jui Ho ,  Ming-Wei Hsu

IPC分类号： G06F15/177

CPC分类号： G06F9/4401

摘要： A computer system has a processor, a basic input and output system (BIOS), a plurality of configurable hardware components, configuration data and an operating system (OS). The method includes executing the plurality of code segments from a starting point of the BIOS for initializing the plurality of hardware components, preparing to receive a configuration request, setting a program interrupt point, switching the computer into a user configuration mode for configuration request, continuing to execute the code segments by the program interrupt point, and loading the operating system.

摘要翻译： 计算机系统具有处理器，基本输入和输出系统（BIOS），多个可配置硬件组件，配置数据和操作系统（OS）。 该方法包括从BIOS的起点执行多个代码段以初始化多个硬件组件，准备接收配置请求，设置程序中断点，将计算机切换到配置请求的用户配置模式，继续 通过程序中断点执行代码段，并加载操作系统。