公开(公告)号：US20050204088A1

公开(公告)日：2005-09-15

申请号：US11051449

申请日：2005-02-04

申请人： Kuan-Jui Ho ,  Stephen Chen ,  Ruei-Ling Lin ,  Chien-Ping Chung

发明人： Kuan-Jui Ho ,  Stephen Chen ,  Ruei-Ling Lin ,  Chien-Ping Chung

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： Data acquisition methods and systems in support of non-snoop transactions. In the data acquisition method, the cache memory is partially written back and invalidate, such that a portion of the data in the cache memory is written back to the DMA buffer. The endpoint device is directed to use a non-snoop transaction to read the data stored in the DMA buffer. The data stored in the DMA buffer is acquired directly without snooping the processor when receiving a non-snoop read transaction.

摘要翻译： 数据采集​​方法和系统支持非侦听事务。 在数据采集方法中，高速缓冲存储器部分地被写回并使其无效，使得高速缓冲存储器中的一部分数据被写回到DMA缓冲器。 端点设备被指示使用非窥探事务来读取存储在DMA缓冲器中的数据。 存储在DMA缓冲器中的数据直接获取，而不会在接收到非窥探读取事务时窥探处理器。

公开(公告)号：US20090235328A1

公开(公告)日：2009-09-17

申请号：US12258428

申请日：2008-10-26

申请人： Tung-Cheng Kuo ,  Ching-Sung Yang ,  Ruei-Ling Lin ,  Cheng-Jye Liu

发明人： Tung-Cheng Kuo ,  Ching-Sung Yang ,  Ruei-Ling Lin ,  Cheng-Jye Liu

IPC分类号： G06F21/00

CPC分类号： G06F21/79

摘要： A data accessing system includes a host and a storage device. The host has a security setup function and includes a first identity code storage block. The host executes the security setup function to set a first identity code according to a second identity code, and the second identity code is stored into the first identity code storage block. The storage device has a security check function and includes a second identity code storage block to store the second identity code, and the storage device executes the security check function to determine if the host is allowed to access the storage device according to the first identity code.

摘要翻译： 数据访问系统包括主机和存储设备。 主机具有安全设置功能，并且包括第一身份码存储块。 主机执行安全设置功能以根据第二身份码设置第一身份码，并且将第二身份码存储到第一身份码存储块中。 存储装置具有安全检查功能，并且包括存储第二身份码的第二身份码存储块，并且存储装置执行安全检查功能，以确定主机是否被允许根据第一身份码访问存储装置 。

公开(公告)号：US07475263B2

公开(公告)日：2009-01-06

申请号：US11404810

申请日：2006-04-17

申请人： Jui-Ming Wei ,  Cheng-Wei Huang ,  Yao-Chun Su ,  Ruei-Ling Lin

发明人： Jui-Ming Wei ,  Cheng-Wei Huang ,  Yao-Chun Su ,  Ruei-Ling Lin

IPC分类号： G06F1/26

CPC分类号： G06F1/3203

摘要： A method for a power management of a central processor unit is disclosed. The method is applied to when the central processor unit is in a low power state without snooping and a bus master signal is sent from a peripheral device. First, a South Bridge sends a control signal to a central processor unit to drive the central processor unit to enter a low power state allowing snooping. Afterward an arbiter of the North Bridge is enabled. If the bus master signal is sent from the peripheral device to the South Bridge, an arbiter of the South Bridge is also enabled. And then the bus master signal is snooped by the central processor unit and the data is transmitted. After the bus master signal is snooped and the data has been transmitted, the arbiters are disabled and the South Bridge drives the central processor unit to return to the low power state without snooping.

摘要翻译： 公开了一种用于中央处理器单元的功率管理的方法。 该方法适用于当中央处理器单元处于低功率状态而没有窥探并且从外围设备发送总线主信号时。 首先，南桥向中央处理器单元发送控制信号，以驱动中央处理器单元进入低功率状态，允许窥探。 之后，启用了北桥的仲裁者。 如果总线主机信号从外围设备发送到南桥，南桥的仲裁器也被使能。 然后由中央处理器单元窥探总线主控信号，并传输数据。 在总线主机信号被窥探并且数据已被传送之后，仲裁器被禁用，并且南桥驱动中央处理器单元返回到低功率状态而不进行窥探。

公开(公告)号：US20080100606A1

公开(公告)日：2008-05-01

申请号：US11554787

申请日：2006-10-31

申请人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

发明人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

IPC分类号： G09G5/00

CPC分类号： G09G5/00 ,  G09G2330/022

摘要： Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

摘要翻译： 包括用于降低计算机系统功耗的系统和方法。 方法的至少一个实施例包括在正常模式下处理数据，接收转换到空闲模式的指示，捕获至少一帧显示数据，以及发送所捕获的显示数据帧以便在 空闲模式

公开(公告)号：US20060239096A1

公开(公告)日：2006-10-26

申请号：US11408141

申请日：2006-04-20

申请人： Hsiu-Ming Chu ,  Kuang-Jui Ho ,  Ruei-Ling Lin

发明人： Hsiu-Ming Chu ,  Kuang-Jui Ho ,  Ruei-Ling Lin

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C11/406 ,  G11C2211/4067

摘要： The present invention relates to a memory-refreshing method applied to a computer system. The computer system includes a central processing unit (CPU), a north bridge chip in communication with the CPU and a system memory in communication with the north bridge chip. The system memory includes at least a first storage zone and a second storage zone. The first storage zone stores a specific data that remains refreshed when the CPU is in a first power-saving mode. The method comprising steps of: refreshing the first storage zone and the second storage zone respectively according to a first clock enable signal and a second clock enable signal generated by the north bridge chip when the CPU is in a normal operation mode; and remaining refreshing the first storage zone according to the first clock enable signal while suspending the second storage zone from being refreshed according to the second clock enable signal when the CPU is in the first power-saving mode

摘要翻译： 本发明涉及应用于计算机系统的存储器刷新方法。 计算机系统包括中央处理单元（CPU），与CPU通信的北桥芯片和与北桥芯片通信的系统存储器。 系统存储器至少包括第一存储区和第二存储区。 当CPU处于第一省电模式时，第一存储区存储保持刷新的特定数据。 该方法包括以下步骤：当CPU处于正常操作模式时，根据第一时钟使能信号和由北桥芯片产生的第二时钟使能信号分别刷新第一存储区和第二存储区; 并且当所述CPU处于所述第一省电模式时，根据所述第一时钟使能信号，根据所述第二时钟使能信号暂停刷新所述第一存储区域，同时暂停所述第二存储区域被刷新

公开(公告)号：US07047336B2

公开(公告)日：2006-05-16

申请号：US10428587

申请日：2003-05-02

申请人： Ruei-Ling Lin ,  Sheng-Chung Wu

发明人： Ruei-Ling Lin ,  Sheng-Chung Wu

IPC分类号： G06F13/00

CPC分类号： G06F13/3625 ,  G06F13/4208 ,  Y02D10/14 ,  Y02D10/151

摘要： A method for blocking a request to a front side bus interconnected between a central processing unit (CPU) and a control chip includes the following steps. First, a bus ownership of the control chip is assigned via a bus priority signal line. Any request from the CPU to the front side bus is blocked when the control chip owns the bus ownership. Meanwhile, any request from the control chip to the front side bus is inhibited when the CPU is blocked from outputting any request to the front side bus.

摘要翻译： 一种用于阻止对中央处理单元（CPU）和控制芯片之间互连的前端总线的请求的方法包括以下步骤。 首先，通过总线优先信号线分配控制芯片的总线所有权。 当控制芯片拥有总线所有权时，从CPU到前端总线的任何请求都将被阻止。 同时，当CPU被阻止向前端总线输出任何请求时，禁止从控制芯片到前端总线的任何请求。

公开(公告)号：US20060095633A1

公开(公告)日：2006-05-04

申请号：US11257260

申请日：2005-10-24

申请人： Ruei-Ling Lin ,  Jiin Lai

发明人： Ruei-Ling Lin ,  Jiin Lai

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/4208 ,  G06F2213/0024

摘要： A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission bandwidth or bus transmission speed.

摘要翻译： 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输带宽或总线传输速度的位数。

公开(公告)号：US6054348A

公开(公告)日：2000-04-25

申请号：US79880

申请日：1998-05-15

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Mong-Song Liang

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Mong-Song Liang

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L29/66659

摘要： A process for creating a semiconductor memory device, featuring the formation of FOX regions, after the creation of a source region, has been developed. The process features a source region, self-aligned to a first set of stacked gate structures, with the subsequent FOX region placed perpendicular to the source region, between a second set of stacked gate structures.

摘要翻译： 已经开发了在创建源区域之后形成FOX区域的半导体存储器件的制造工艺。 该过程的特征在于源区域与第一组堆叠的栅极结构自对准，随后的FOX区域垂直于源区域放置在第二组堆叠栅极结构之间。

公开(公告)号：US07782313B2

公开(公告)日：2010-08-24

申请号：US11554787

申请日：2006-10-31

申请人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

发明人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

IPC分类号： G09G5/36 ,  G06F1/00

CPC分类号： G09G5/00 ,  G09G2330/022

摘要： Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

摘要翻译： 包括用于降低计算机系统功耗的系统和方法。 方法的至少一个实施例包括在正常模式下处理数据，接收转换到空闲模式的指示，捕获至少一帧显示数据，以及发送所捕获的显示数据帧以便在 空闲模式

公开(公告)号：US07757031B2

公开(公告)日：2010-07-13

申请号：US11876579

申请日：2007-10-22

申请人： Ruei-Ling Lin ,  Jiin Lai

发明人： Ruei-Ling Lin ,  Jiin Lai

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F7/38

CPC分类号： G06F13/4217

摘要： A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

摘要翻译： 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输宽度或总线传输速度。