公开(公告)号：US20150188551A1

公开(公告)日：2015-07-02

申请号：US14145493

申请日：2013-12-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Amaresh V. Malipatil

IPC: H03L7/087 ,  H03L7/06

CPC classification number: H03L7/087 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/093 ,  H04L7/0058 ,  H04L7/033

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。

公开(公告)号：US08831142B2

公开(公告)日：2014-09-09

申请号：US13717973

申请日：2012-12-18

Applicant: LSI Corporation

Inventor： Shiva Prasad Kotagiri ,  Pervez M. Aziz ,  Amaresh V. Malipatil

IPC: H04L27/00 ,  H04L27/01

CPC classification number: H04L25/063

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈环路中的控制器取消，以根据数据判定误差信号或用于时钟恢复的定时信号产生补偿信号。