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1.发明授权Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains 有权使用抖动频率相关量化阈值和环路增益的量化相位误差样本的时钟恢复公开(公告)号：US09397674B2
公开(公告)日：2016-07-19
申请号：US14145493
申请日：2013-12-31
Applicant: LSI Corporation
Inventor： Pervez M. Aziz , Shiva Prasad Kotagiri , Sundeep Venkatraman , Sunil Srinivasa , Amaresh V. Malipatil
CPC classification number: H03L7/087 , H03L7/06 , H03L7/0807 , H03L7/0814 , H03L7/093 , H04L7/0058 , H04L7/033
Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.
Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。
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2.发明申请CLOCK RECOVERY USING QUANTIZED PHASE ERROR SAMPLES USING JITTER FREQUENCY-DEPENDENT QUANTIZATION THRESHOLDS AND LOOP GAINS 有权使用抖动频率依赖量化阈值和环路增益的定量相位误差样本的时钟恢复公开(公告)号：US20150188551A1
公开(公告)日：2015-07-02
申请号：US14145493
申请日：2013-12-31
Applicant: LSI Corporation
Inventor： Pervez M. Aziz , Shiva Prasad Kotagiri , Sundeep Venkatraman , Sunil Srinivasa , Amaresh V. Malipatil
CPC classification number: H03L7/087 , H03L7/06 , H03L7/0807 , H03L7/0814 , H03L7/093 , H04L7/0058 , H04L7/033
Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.
Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。
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公开(公告)号：US08831142B2
公开(公告)日：2014-09-09
申请号：US13717973
申请日：2012-12-18
Applicant: LSI Corporation
Inventor： Shiva Prasad Kotagiri , Pervez M. Aziz , Amaresh V. Malipatil
CPC classification number: H04L25/063
Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.
Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈环路中的控制器取消，以根据数据判定误差信号或用于时钟恢复的定时信号产生补偿信号。
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Patent Agency Ranking
4.发明授权Single serdes transmitter driver design for both ethernet and peripheral component interconnect express applications 有权用于以太网和外围组件互连的单一serdes发射机驱动程序设计表示应用公开(公告)号：US08989254B2
公开(公告)日：2015-03-24
申请号：US13851502
申请日：2013-03-27
Applicant: LSI Corporation
Inventor： Tai Jing , Lijun Li , Shiva Prasad Kotagiri
CPC classification number: G06F13/102 , H04L25/03878
Abstract: An apparatus includes a first coding circuit, a second coding circuit, and a plurality of source series terminated driver slices. The first coding circuit may be configured to generate a plurality of digital filter control codes in response to a plurality of filter coefficients and a control signal. The control signal selects between a plurality of communication specifications. The second coding circuit may be configured to generate a plurality of driver slice control codes in response to the plurality of digital filter control codes. The plurality of source series terminated driver slices configured to generate an output signal according to a selected one of the plurality of communication specifications in response to the plurality of driver slice control codes, a main cursor signal, a pre-cursor signal, and a post cursor signal.
Abstract translation: 一种装置包括第一编码电路，第二编码电路和多个源极序列终止的驱动器片。 第一编码电路可以被配置为响应于多个滤波器系数和控制信号而生成多个数字滤波器控制码。 控制信号在多个通信规格之间进行选择。 第二编码电路可以被配置为响应于多个数字滤波器控制代码而产生多个驱动器片控制代码。 所述多个源极序列终止的驱动器片被配置为响应于所述多个驱动器片控制代码，主光标信号，前置光标信号和柱子，根据所述多个通信规范中的所选择的一个生成输出信号 光标信号。
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公开(公告)号：US20150381393A1
公开(公告)日：2015-12-31
申请号：US14315759
申请日：2014-06-26
Applicant: LSI Corporation
Inventor： Shiva Prasad Kotagiri , Pervez M. Aziz , Amaresh V. Malipatil
CPC classification number: H04L25/03057 , H04L7/033 , H04L7/0331 , H04L25/0292 , H04L25/0307 , H04L25/03159 , H04L25/03885 , H04L2025/03636 , H04L2025/037
Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.
Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈环路中的控制器取消，以根据数据判定误差信号或用于时钟恢复的定时信号产生补偿信号。
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公开(公告)号：US20150103961A1
公开(公告)日：2015-04-16
申请号：US14053069
申请日：2013-10-14
Applicant: LSI Corporation
Inventor： Amaresh V. Malipatil , Shiva Prasad Kotagiri , Sundeep Venkatraman , Sunil Srinivasa , Pervez M. Aziz
CPC classification number: H04B1/10 , H04B1/30 , H04L7/0016 , H04L7/0278 , H04L25/03038
Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.
Abstract translation: 一种在数据接收机等中使用的频带估计器，用于增强接收机中的时钟和数据恢复装置（CDR）的正弦抖动容限。 检测器使用两个不同抽头长度的移动平均滤波器，其接收来自CDR内的增益控制信号。 来自移动平均滤波器的输出信号被处理以通过测量在每个输出信号的转换之间发生的数字时钟周期来确定每个输出信号的半波时间周期。 将最长半波周期的时钟周期数与表示各种频带的频率限制的多个值进行比较，以确定哪个频带将抖动分类为增益控制信号。 确定的频带用于从查找表中选择一组用于CDR中的增益值。
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7.发明申请SINGLE SERDES TRANSMITTER DRIVER DESIGN FOR BOTH ETHERNET AND PERIPHERAL COMPONENT INTERCONNECT EXPRESS APPLICATIONS 有权用于以太网和外围组件互连应用的单个SERDES发射机驱动程序设计公开(公告)号：US20140181845A1
公开(公告)日：2014-06-26
申请号：US13851502
申请日：2013-03-27
Applicant: LSI CORPORATION
Inventor： Tai Jing , Lijun Li , Shiva Prasad Kotagiri
IPC: G06F13/10
CPC classification number: G06F13/102 , H04L25/03878
Abstract: An apparatus includes a first coding circuit, a second coding circuit, and a plurality of source series terminated driver slices. The first coding circuit may be configured to generate a plurality of digital filter control codes in response to a plurality of filter coefficients and a control signal. The control signal selects between a plurality of communication specifications. The second coding circuit may be configured to generate a plurality of driver slice control codes in response to the plurality of digital filter control codes. The plurality of source series terminated driver slices configured to generate an output signal according to a selected one of the plurality of communication specifications in response to the plurality of driver slice control codes, a main cursor signal, a pre-cursor signal, and a post cursor signal.
Abstract translation: 一种装置包括第一编码电路，第二编码电路和多个源极序列终止的驱动器片。 第一编码电路可以被配置为响应于多个滤波器系数和控制信号而生成多个数字滤波器控制码。 控制信号在多个通信规格之间进行选择。 第二编码电路可以被配置为响应于多个数字滤波器控制代码而产生多个驱动器片控制代码。 所述多个源极序列终止的驱动器片被配置为响应于所述多个驱动器片控制代码，主光标信号，前置光标信号和柱子，根据所述多个通信规范中的所选择的一个生成输出信号 光标信号。
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公开(公告)号：US20140169440A1
公开(公告)日：2014-06-19
申请号：US13717973
申请日：2012-12-18
Applicant: LSI CORPORATION
Inventor： Shiva Prasad Kotagiri , Pervez M. Aziz , Amaresh V. Malipatil
CPC classification number: H04L25/063
Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.
Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈回路中的控制器取消，以根据数据判定误差信号或用于停机恢复的定时信号产生补偿信号。
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