公开(公告)号：US09047882B2

公开(公告)日：2015-06-02

申请号：US14015126

申请日：2013-08-30

Applicant: LSI Corporation

Inventor： Lu Pan ,  Lu Lu ,  Haitao Xia

IPC: G11B5/09 ,  G11B5/012 ,  G11B20/18

CPC classification number: G11B5/09 ,  G11B5/012 ,  G11B20/1833

Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

Abstract translation: 存储系统包括可操作以维持数据组的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以对存储介质进行编码的多电平编码器 数据在被写入存储介质之前以多种不同的代码率进行设置;以及多级解码器，其可操作以对从存储介质检索的数据集进行解码，并且在解码编码的值时应用以较低码率编码的解码值 以更高的代码率。

公开(公告)号：US08995072B1

公开(公告)日：2015-03-31

申请号：US14135984

申请日：2013-12-20

Applicant: LSI Corporation

Inventor： Dahua Qin ,  Xun Zhang ,  Lu Lu ,  Haitao Xia ,  Jianzhong Huang

IPC: G11B5/09 ,  G11B27/36 ,  G11B21/02 ,  G11B5/596

CPC classification number: G11B5/09 ,  G11B5/59611 ,  G11B5/59688 ,  G11B20/10009

Abstract: A servo system includes a detector circuit operable to apply a data detection algorithm to digital data to yield hard decisions, a convolution circuit operable to yield ideal digital data based on the hard decisions and on target values, a subtraction circuit operable to subtract the ideal digital data from the digital data to yield an error signal, a scaling circuit operable to scale the error signal to yield a scaled noise signal, an adder operable to add the scaled noise signal to the digital data to yield noise-added digital data, and a second detector circuit operable to apply a second data detection algorithm to the noise-added digital data to yield output hard decisions.

Abstract translation: 伺服系统包括检测器电路，可操作以将数据检测算法应用于数字数据以产生硬判决，卷积电路可操作以基于硬判决和目标值产生理想数字数据，减法电路可操作以减去理想数字 来自数字数据的数据以产生误差信号，缩放电路，可操作以缩放误差信号以产生缩放的噪声信号;加法器，可操作以将缩放的噪声信号添加到数字数据以产生噪声附加的数字数据;以及 第二检测器电路可操作以将第二数据检测算法应用于经噪声增加的数字数据以产生输出硬判决。

公开(公告)号：US08976476B1

公开(公告)日：2015-03-10

申请号：US14250587

申请日：2014-04-11

Applicant: LSI Corporation

Inventor： Lu Lu ,  Haitao Xia ,  Ku Hong Jeong ,  Yuqing Yang

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B20/1217 ,  G11B20/1866

Abstract: A hard disk drive or other storage device comprises a storage medium, a read/write head, and read channel circuitry coupled to the read/write head. The read channel circuitry comprises a despreader configured to generate a stitched logic sector by stitching together subsectors of that logic sector that were interleaved with subsectors of other logic sectors for storage on the storage medium, and a subsector bridging control module configured to control a number of bridging bits inserted by the despreader between a given pair of adjacent subsectors of the stitched logic sector. The subsector bridging control module may be illustratively configured to cause the despreader to insert a sufficient number of bridging bits between each pair of adjacent subsectors of the stitched logic sector so as to prevent discontinuities that might otherwise arise from use of X-averaging in generation of Y samples from X samples in a retry mode of operation.

Abstract translation: 硬盘驱动器或其他存储设备包括耦合到读/写头的存储介质，读/写头和读通道电路。 所述读通道电路包括解扩器，其被配置为通过将与所述逻辑扇区交错的所述逻辑扇区的子部分拼接在一起来生成缝合的逻辑扇区，用于存储在所述存储介质上的其他逻辑扇区的子部门，以及子网桥接控制模块， 由解扩器插入的在缝合逻辑扇区的给定对相邻子部分之间的桥接位。 子部门桥接控制模块可以被示意性地配置为使解扩器在缝合逻辑扇区的每对相邻子部分之间插入足够数量的桥接位，以便防止在产生X平均时可能由于使用X平均而产生的不连续性 在重试操作模式下从X个样本获取Y个样本。

公开(公告)号：US08867156B2

公开(公告)日：2014-10-21

申请号：US13798638

申请日：2013-03-13

Applicant: LSI Corporation

Inventor： Fan Zhang ,  Lu Lu ,  Jun Xiao ,  Haitao Xia ,  Shaohua Yang ,  Rui Cao ,  Shu Li

IPC: G11B20/10 ,  G06F12/08

CPC classification number: G06F12/082 ,  G06F12/0802 ,  G11B20/10 ,  G11B20/10361 ,  G11B20/10527

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于基于优先级的数据处理的系统和方法。

公开(公告)号：US08854760B1

公开(公告)日：2014-10-07

申请号：US13886170

申请日：2013-05-02

Applicant: LSI Corporation

Inventor： Lu Lu ,  Haitao Xia ,  Jianzhong Huang

IPC: G11B5/09 ,  G11B20/18

CPC classification number: G11B20/18 ,  G11B20/10388

Abstract: A data processing circuit includes a subtraction circuit operable to subtract an ideal version of a data pattern from a sampled version of a data pattern to yield a difference signal, an error calculation circuit operable to calculate an error between the ideal version of the data pattern and the sampled version of the data pattern based on the difference signal, and a comparator circuit operable to compare the error with a threshold value and operable to assert a track refresh signal if the error is greater than the threshold value. The track refresh signal is operable to trigger a magnetic storage device to refresh data on a data track.

Abstract translation: 数据处理电路包括减法电路，其可操作以从数据模式的采样版本中减去数据模式的理想版本以产生差分信号;误差计算电路，用于计算数据模式的理想版本与 基于差分信号的数据模式的采样版本;以及比较器电路，其可操作以将误差与阈值进行比较，并且如果误差大于阈值则可用于断言轨迹刷新信号。 轨道刷新信号可操作以触发磁存储设备来刷新数据轨道上的数据。

公开(公告)号：US20140254041A1

公开(公告)日：2014-09-11

申请号：US13832503

申请日：2013-03-15

Applicant: LSI CORPORATION

Inventor： Lu Lu ,  Haitao Xia ,  Bruce A. Wilson

IPC: G11B20/10

CPC classification number: G11B20/10305 ,  G11B20/10009 ,  G11B20/10296 ,  G11B20/10509 ,  G11B2020/1298 ,  G11B2220/2516

Abstract: Servo channel noise limits are defined through Viterbi decisions based on servo gate signals. Y values are used to produce a first Viterbi decision at each servo gate. Viterbi decisions and Y values are used to produce ideal Y values. Y values and ideal Y values are used to produce an error value which is adjusted by a noise factor based on estimated channel characteristics. The noise value is combined with Y values and used to produce a second Viterbi decision at each servo gate.

Abstract translation: 通过基于伺服门信号的维特比决定来定义伺服信道噪声限制。 Y值用于在每个伺服门产生第一维特比（Viterbi）决定。 维特比决策和Y值用于产生理想的Y值。 Y值和理想Y值用于产生基于估计的信道特性由噪声因子调整的误差值。 噪声值与Y值组合，用于在每个伺服门产生第二维特比（Viterbi）判定。