公开(公告)号：US20130146986A1

公开(公告)日：2013-06-13

申请号：US13324740

申请日：2011-12-13

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L27/092 ,  H01L27/088

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US20190326219A1

公开(公告)日：2019-10-24

申请号：US16502521

申请日：2019-07-03

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285 ,  H01L27/02 ,  H01L21/768

摘要： A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US08823178B2

公开(公告)日：2014-09-02

申请号：US13617853

申请日：2012-09-14

申请人： Juhan Kim ,  Mahbub Rashed

发明人： Juhan Kim ,  Mahbub Rashed

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L23/5386 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

摘要翻译： 公开了一种提供具有双图案化金属层结构的SRAM位单元的方法。 实施例包括：经由第一图案化工艺提供字线结构，接地线结构，电力线结构或其组合; 以及经由第二图案化处理提供靠近所述字线结构，所述接地线结构，所述电力线结构或其组合的位线结构。 实施例包括：提供作为字线结构的第一着陆焊盘和作为接地线结构的第二着陆焊盘; 以及提供所述第一着陆垫具有第一末端边缘和第一侧边缘，并且所述第二着陆垫具有第二末端边缘和第二侧边缘，其中所述第一侧边缘面向所述第二侧边缘。

公开(公告)号：US20140027918A1

公开(公告)日：2014-01-30

申请号：US13561932

申请日：2012-07-30

申请人： Mahbub Rashed ,  Marc Tarabbia ,  Chinh Nguyen ,  David Doman ,  Juhan Kim ,  Xiang Qi ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Marc Tarabbia ,  Chinh Nguyen ,  David Doman ,  Juhan Kim ,  Xiang Qi ,  Suresh Venkatesan

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/5381 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/768 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11861 ,  H01L2027/11874 ,  H01L2924/0002 ,  Y02P90/265 ,  Y02T10/82 ,  H01L2924/00

摘要： An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

摘要翻译： 公开了一种使用扩散接触结构提供基于交叉耦合的设计的方法。 实施例包括在衬底上提供第一和第二栅极结构; 提供跨越第一栅极结构的第一栅极截止区域和穿过第二栅极结构的第二栅极截止区域; 在所述第一栅极结构上提供第一栅极接触，以及在所述第二栅极结构上方的第二栅极接触; 以及在所述第一和第二栅极切割区域之间提供扩散接触结构，以将所述第一栅极接触耦合到所述第二栅极接触。

公开(公告)号：US09355910B2

公开(公告)日：2016-05-31

申请号：US13324740

申请日：2011-12-13

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/70 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US08618607B1

公开(公告)日：2013-12-31

申请号：US13539830

申请日：2012-07-02

申请人： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/02

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

摘要翻译： 本文公开的一个说明性器件包括限定在半导体衬底中的连续有源区，形成在连续有源区中和上方的第一和第二晶体管，第一和第二晶体管中的每一个包括形成在连续有源区中的多个掺杂区， 导电隔离电极位于第一和第二晶体管之间的连续有源区上方，导电隔离电极与导电隔离电极导电耦合。

公开(公告)号：US20060220717A1

公开(公告)日：2006-10-05

申请号：US11097659

申请日：2005-04-01

申请人： Milind Padhye ,  Yuan Yuan ,  Mahbub Rashed

发明人： Milind Padhye ,  Yuan Yuan ,  Mahbub Rashed

IPC分类号： H03K3/00

CPC分类号： H03K3/0375

摘要： A flip-flop (10) comprises a first latch circuit (18), a second latch circuit (24), and a third latch circuit (26). The first latch circuit (18) is coupled to receive a clock signal and a first power supply voltage. The second latch circuit (24) is coupled to the first latch circuit (18) and receives the clock signal and the first power supply voltage. Preparatory to entering a low power mode, the third latch circuit (26) receives a second power supply voltage and is coupled to the second latch circuit (24) in response to a power down signal. During the low power mode, the first power supply voltage is removed from the first and second latch circuits (18, 24). When returning to a normal operating mode, the first power supply voltage is provided to the first and second latch circuits (18, 24), and the third latch circuit (26) is coupled to the first latch circuit (18) in response to a power restore signal.

摘要翻译： 触发器（10）包括第一锁存电路（18），第二锁存电路（24）和第三锁存电路（26）。 第一锁存电路（18）被耦合以接收时钟信号和第一电源电压。 第二锁存电路（24）耦合到第一锁存电路（18）并接收时钟信号和第一电源电压。 准备进入低功率模式，第三锁存电路（26）响应于掉电信号接收第二电源电压并耦合到第二锁存电路（24）。 在低功率模式期间，从第一和第二锁存电路（18,24）去除第一电源电压。 当返回到正常操作模式时，第一电源电压被提供给第一和第二锁存电路（18,24），并且第三锁存电路（26）响应于第一锁存电路 电源恢复信号。

公开(公告)号：US20060220726A1

公开(公告)日：2006-10-05

申请号：US11098344

申请日：2005-04-04

申请人： Gregory Ward ,  Mohamed Moosa ,  Mahbub Rashed

发明人： Gregory Ward ,  Mohamed Moosa ,  Mahbub Rashed

IPC分类号： H03K3/01

CPC分类号： H03K19/0016 ,  H03K19/0027

摘要： A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.

摘要翻译： 良好偏置系统通过集成电路（IC）将良好偏置设置点动态调整到最佳电平，从而在待机或低功耗工作模式下实现更高的功率节省和部件可靠性。 IC内部的一个控制器确定芯片电源电压在即将到来的待机或低功耗模式下是否会降低，并且设置一个控制负的良好偏置设置点的寄存器，以便将相位偏差充分提供给IC的电荷阱。 为了最小化漏电流而不损害可靠性，如果要对IC施加降低的电源电压，则将偏置设定点设置为（1）最佳阱偏置设定点，或（2）最小阱偏置集 当要向IC施加额定电压或高电源电压时。