公开(公告)号：US20070200840A1

公开(公告)日：2007-08-30

申请号：US11674029

申请日：2007-02-12

申请人： Steven D. Clynes ,  Liming Xiu

发明人： Steven D. Clynes ,  Liming Xiu

IPC分类号： G09G5/00

CPC分类号： G09G5/363 ,  G09G5/008

摘要： A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b, 22c, 22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr). The numbers of times that the difference voltages exceed the threshold voltage over a field or frame is analyzed according to various techniques, to determine whether and in which direction to adjust the position of the current sample clock phase within the pixel period.

摘要翻译： 公开了一种数字视频系统（2），其中模拟输入视频信号在最佳采样相位（P SUB）处采样，并被转换成数字数据流进行显示。 锁相环（12）产生多个采样时钟相位。 其中一个采样时钟相位（P nc）被应用于模拟数字转换器（10），其相应地对模拟输入视频信号进行数字化。 提供了相位对准电路（20），其包括与模数转换器（10）并联采样模拟输入视频信号的三个采样和保持电路（22b，22c，22a） 在模数转换器（10）使用的当前采样时钟相位之前，之中和之后的时间。 将较早和较晚采样的电压与电流采样电压进行比较，以产生差分电压，每个差值电压与阈值电压（V SUB）之间进行比较。 根据各种技术分析差分电压超过场或帧上的阈值电压的次数，以确定在像素周期内是否以及在哪个方向调整当前采样时钟相位的位置。

公开(公告)号：US20070055718A1

公开(公告)日：2007-03-08

申请号：US11221674

申请日：2005-09-07

申请人： Gonggui Xu ,  Haydar Bilhan ,  Liming Xiu

发明人： Gonggui Xu ,  Haydar Bilhan ,  Liming Xiu

IPC分类号： G06F1/02

CPC分类号： G06F1/025

摘要： An apparatus employing control words to present a synthesized output signal having an output frequency and a delay with respect to an input signal includes: (a) A multiplexer receiving the input signal and having an output and an address input. (b) An output unit generates the output signal in response to a drive signal from the multiplexer. (c) A first register coupled with the multiplexer output. (d) A second register coupled with the multiplexer and the first register. The first register responds to a multiplexer output signal to provide a first control signal to the second register based upon the control words. The second register responds to the multiplexer output signal to provide a second control signal to the address input based upon the first control signal and the control words. The multiplexer presents the drive signal in response to the second control signal.

摘要翻译： 一种采用控制字呈现具有输出频率和相对于输入信号的延迟的合成输出信号的装置包括：（a）多路复用器，接收输入信号并具有输出和地址输入。 （b）输出单元响应于来自多路复用器的驱动信号产生输出信号。 （c）与多路复用器输出耦合的第一寄存器。 （d）与复用器和第一寄存器耦合的第二寄存器。 第一寄存器响应多路复用器输出信号，以基于控制字向第二寄存器提供第一控制信号。 第二寄存器响应多路复用器输出信号，以基于第一控制信号和控制字向地址输入提供第二控制信号。 复用器响应于第二控制信号呈现驱动信号。

公开(公告)号：US20060256119A1

公开(公告)日：2006-11-16

申请号：US11187313

申请日：2005-07-21

申请人： Liming Xiu ,  Wen Li ,  Xiaopeng Li

发明人： Liming Xiu ,  Wen Li ,  Xiaopeng Li

IPC分类号： G06F13/14

CPC分类号： G09G5/008

摘要： A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and a signal containing a synchronization waveform for the image. An analog-to-digital converter (ADC) receives the analog signal and converts it to a sampled digital waveform. A phase-locked loop including a programmable frequency divider controls the sampling time for the ADC. The programmable frequency divider is controlled by a dividing-ratio algorithm that selects a dividing ratio, measures the number of pixels in a video line using the dividing ratio, and recomputes the dividing ratio by multiplying the selected dividing ratio by the expected number of pixels in a video line and dividing by the measured number of pixels. The sampling phase for the ADC is selected by a sampling-phase control algorithm that minimizes a function representative of the flatness of the sampled digital waveform.

公开(公告)号：US09036755B2

公开(公告)日：2015-05-19

申请号：US13630988

申请日：2012-09-28

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H04L7/00 ,  H03L7/08 ,  H04L7/033 ,  H03L7/099 ,  H03L7/091

CPC分类号： H03L7/0807 ,  H03L7/091 ,  H03L7/0991 ,  H04L7/0331

摘要： A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.

摘要翻译： 时钟数据恢复电路包括被配置为接收输入数据信号和恢复时钟的二进制相位检测器，并输出相位偏移信号和恢复数据; 数字环路控制电路，被配置为接收所述相位偏移信号并输出​​控制信号; 以及数字频率发生器，被配置为接收所述控制信号并输出​​恢复的时钟。 一种时钟恢复方法包括从输入数据和反馈时钟信号产生数字相位偏移信号; 从相位偏移信号产生时钟频率控制信号; 响应于所述控制信号产生恢复的时钟; 当数字相位偏移信号具有第一二进制状态时，减慢恢复的时钟; 当数字相位偏移信号具有第二二进制状态时，加速恢复时钟; 并且当数字相位偏移信号具有第三二进制状态时保持恢复的时钟。

公开(公告)号：US09008261B2

公开(公告)日：2015-04-14

申请号：US13741118

申请日：2013-01-14

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H03K21/00 ,  G06F1/08 ,  H03K23/66 ,  H03K23/68

CPC分类号： G06F1/08 ,  H03K23/667 ,  H03K23/68

摘要： An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

摘要翻译： 一种开环时钟分频器电路包括：（a）第一分频器，被配置为接收输入时钟信号并输出​​第一分频时钟信号;（b）飞加法器合成器，被配置为对第一分频时钟信号进行分数分频并输出分数 时钟信号，和（c）第二分频器，被配置为接收分数分时钟信号并输出​​第二分频时钟信号。 开环时钟分频器电路有利地提供了在源频率（fs）和目的频率（fd）之间没有反馈回路的分数分频器。 还公开了产生涉及开环时钟分频器电路的分频时钟信号的方法。

公开(公告)号：US20080021944A1

公开(公告)日：2008-01-24

申请号：US11489982

申请日：2006-07-20

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： G06F1/02

CPC分类号： G06F1/025 ,  H03L7/18

摘要： A method for reducing jitter in an output signal from a frequency synthesizer using a control word having a fractional bit includes dividing the output signal by a predetermined divisor to present a modified output signal substantially free of jitter.

摘要翻译： 使用具有分数位的控制字来减少来自频率合成器的输出信号中的抖动的方法包括将输出信号除以预定的除数以呈现基本上没有抖动的修改的输出信号。

公开(公告)号：US06940937B2

公开(公告)日：2005-09-06

申请号：US10026489

申请日：2001-12-24

申请人： Liming Xiu ,  Zhihong You

发明人： Liming Xiu ,  Zhihong You

IPC分类号： H03K5/00 ,  H03L7/099 ,  H03L7/16 ,  H03D3/24

CPC分类号： H03L7/16 ,  H03K2005/00208 ,  H03L7/0996

摘要： A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed implementation of the phase-locked loop (25) includes a voltage-controlled oscillator (30) having an even number of differential stages (31) to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit (27) includes two adder legs that generate select signals applied to first and second multiplexers (40a, 40b), for selecting among the clock phases from the voltage-controlled oscillator (30). The outputs of the first and second multiplexers (40a, 40b) are applied to a two-to-one multiplexer (46) which is controlled by the output clock signal (CLK1), to drive clock edges to a T flip-flop (48) to produce the output clock signals (CLK1, CLK2). In another embodiment, more than two adder and register units (55) control corresponding multiplexers (56) for selecting clock phases from the voltage-controlled oscillator (30) for application to an output multiplexer (58), which is controlled by a clock control circuit (60) to apply the selected clock phases to the T flip-flop (62). In another embodiment, primary and phase-shifted frequency synthesis circuits (227, 327) receive initialization values (INIT1, INIT2) that establish the phase differential and ensure proper initialization.

摘要翻译： 公开了一种包括锁相环（25）和一个或多个频率合成电路（27; 77; 227; 237）的时钟合成电路（22）。 所公开的锁相环（25）的实现包括具有偶数个差分级（31）的压控振荡器（30），以产生偶数等间隔的时钟相位。 在一种布置中，频率合成电路（27）包括两个加法器支路，其产生施加到第一和第二多路复用器（40a，40b）的选择信号，用于在来自压控振荡器（30）的时钟相位之间进行选择。 第一和第二多路复用器（40a，40b）的输出被施加到由输出时钟信号（CLK 1）控制的二对一复用器（46），以将时钟边缘驱动到T触发器 （48）以产生输出时钟信号（CLK 1，CLK 2）。 在另一实施例中，多于两个的加法器和寄存器单元（55）控制相应的多路复用器（56），用于从压控振荡器（30）中选择时钟相位，用于施加到输出多路复用器（58），其由时钟控制 电路（60）将所选择的时钟相位施加到T触发器（62）。 在另一个实施例中，初级和相移频率合成电路（227,327）接收建立相位差并初始化的初始化值（INIT 1，INIT 2）。

公开(公告)号：US20050162552A1

公开(公告)日：2005-07-28

申请号：US10829770

申请日：2004-04-22

申请人： Liming Xiu ,  Jason Meiners

发明人： Liming Xiu ,  Jason Meiners

IPC分类号： H03L7/00 ,  H04N5/06

CPC分类号： H03L7/00

摘要： A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency synthesis circuit (74S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit (74), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit (74′) architecture, in combination with a phase signal (PH) generated by a digital controller (61). Multiple phase-tuned sample clocks (PIX_CLK_A, PIX_CLK_B, PIX_CLK_C) can be similarly generated from multiple flying-adder frequency synthesis circuits (174A, 174B, 174C), each controlled by the frequency control word (FREQ) and a corresponding phase signal (PHA, PHB, PHC). Video mode control logic (65, 165) can also be implemented by way of a similar DCO architecture. The DCO (60) may be used to generate a clock signal at a large frequency multiple relative to the input signal, outside of the video decoder context.

摘要翻译： 公开了一种包括数字控制振荡器（DCO）（60,160）的视频解码器（52,152）。 DCO（60,160）包括测量输入信号频率（例如输入视频信号的水平同步频率）的第一飞行加法器频率合成电路（74S）。 响应于该输入信号频率产生频率控制字（FREQ），并将其施加到第二飞行加法器频率合成电路（74），该第二飞行加法器频率合成电路又选择输出时钟信号的前沿和后沿的适当相位 （PIX_CLK）。 输出时钟信号（PIX_CLK）的相位调谐可以通过与由数字控制器（61）产生的相位信号（PH）结合使用替代的飞行加法器频率合成电路（74'）架构来实现。 多个相位调制的采样时钟（PIX_CLK_A，PIX_CLK_B，PIX_CLK_C）可以类似地从多个飞越加法器频率合成电路（174A，174B，174C）产生，每个由频率控制字（FREQ）控制的相应相位 信号（PHA，PHB，PHC）。 视频模式控制逻辑（65,165）也可以通过类似的DCO架构来实现。 DCO（60）可用于在视频解码器上下文之外产生相对于输入信号大的频率倍数的时钟信号。

公开(公告)号：US10686458B1

公开(公告)日：2020-06-16

申请号：US15665579

申请日：2017-08-01

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H03K4/26 ,  H03L7/18 ,  H03L7/099 ,  H03L7/093

摘要： A TAF-DPS based circuits and methods to improve electronic system's frequency accuracy and enhance its frequency stability is disclosed in this application. Present invention creates a circuit architecture and a calculation scheme for compensating frequency source's frequency error. Present invention further discloses a method of incorporating said scheme into functional chip built in either ASIC or FPGA fashion. Present invention further presents a method of using TAF-DPS-frequency-compensation-scheme-equipped-chips as nodes in electronic network. As a result, the circuit and apparatus disclosed in present invention can improve electronic system's performance from the time synchronization perspective.

公开(公告)号：US09118275B1

公开(公告)日：2015-08-25

申请号：US14088500

申请日：2013-11-25

申请人： Liming Xiu

发明人： Liming Xiu

IPC分类号： H03B21/00 ,  H03B21/02

CPC分类号： H03B21/02 ,  G06F1/08

摘要： An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides. A method of creating such adaptive clock generation circuit is also presented.

摘要翻译： 一种用于以动态方式合成时间平均频率的自适应时钟产生电路包括：（a）用于产生固定时间跨度的基本单元的定时电路，（b）从微电子系统接收输入的控制电路，其中控制电路和 时钟生成电路用于产生更新信号和频率控制字，（c）用于通过利用所述基本单元和频率控制字来产生多种类型的脉冲的直接周期合成器，用于创建时钟段 通过根据更新信号连接从所述多种类型中选择的串联电脉冲，用于通过串联连接所述段来创建整个时钟脉冲串。 所得到的时钟脉冲串的时间 - 频率与时钟发生电路所在的微电子系统的操作所需的选定频率相匹配。 还提出了一种创建这种自适应时钟发生电路的方法。