公开(公告)号：US20230010161A1

公开(公告)日：2023-01-12

申请号：US17369992

申请日：2021-07-08

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo

IPC: H04L12/863 ,  H04L12/861

Abstract: A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

公开(公告)号：US20220350756A1

公开(公告)日：2022-11-03

申请号：US17306033

申请日：2021-05-03

Applicant: Mellanox Technologies LTD.

Inventor： Idan Burstein ,  Ilan Pardo ,  Yamin Friedman ,  Michael Cotsford ,  Mark Rosenbluth ,  Hillel Chapman

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/38 ,  G06F12/02 ,  G06F12/0811 ,  G06F15/78

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

公开(公告)号：US10394747B1

公开(公告)日：2019-08-27

申请号：US15609433

申请日：2017-05-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Carl G. Ramey ,  Gil Moran ,  Adi Menachem ,  Christopher J. Jackson ,  Ilan Pardo ,  Ariel Shahar ,  Tzuriel Katoa

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.